Datasheet

MCP3911
DS20002286B-page 20  2012-2013 Microchip Technology Inc.
3.4 ADC Differential Analog inputs
(CHn+/CHn-)
The two fully differential analog voltage inputs for the
Delta-Sigma ADCs are:
• CH0 and CH0+
• CH1 and CH1+
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mV/GAIN with
V
REF
=1.2V.
The maximum differential voltage is proportional to the
V
REF
voltage. The maximum absolute voltage, with
respect to A
GND
, for each CHn+/- input pin is ±1V with
no distortion, and ±2V with no breaking after
continuous voltage. This maximum absolute voltage is
not proportional to the V
REF
voltage.
3.5 Analog Ground (A
GND
)
A
GND
is the ground connection to internal analog
circuitry (see the “Functional Block Diagram”). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as D
GND
, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this pin is tied to this
Printed Circuit Board (PCB) plane. This plane should
also reference all other analog circuitry in the system.
3.6 Non-Inverting Reference Input,
Internal Reference Output
(REFIN+/OUT)
This pin is the non-inverting side of the differential
voltage reference input for both ADCs or the internal
voltage reference output.
When VREFEXT = 1, an external voltage reference
source can be used and the internal voltage reference
is disabled. When using an external differential voltage
reference, it should be connected to its V
REF+
pin.
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT = 0, the internal voltage reference is
enabled and connected to this pin through a switch. If
used as a voltage source, this voltage reference has a
minimal drive capability and thus needs proper
buffering and bypass capacitances. A 0.1 µF ceramic
capacitor is sufficient in most cases.
If the voltage reference is only used as an internal
V
REF
, adding bypass capacitance on REFIN+/OUT is
not necessary for keeping ADC accuracy. If left floating,
a minimal 0.1 µF ceramic capacitance can be
connected to avoid EMI/EMC susceptibility issues due
to the antenna created by the REFIN+/OUT pin.
3.7 Inverting Reference Input (REFIN-)
This pin is the inverting side of the differential voltage
reference input for both ADCs. When using an external
differential voltage reference, it should be connected to
its V
REF-
pin. When using an external single-ended
voltage reference or when VREFEXT = 0 (Default) and
using the internal voltage reference, this pin should be
directly connected to A
GND
.
3.8 Digital Ground Connection (D
GND
)
D
GND
is the ground connection to the internal digital
circuitry (see Functional Block Diagram). To ensure
optimal accuracy and noise cancellation, D
GND
must
be connected to the same ground as A
GND
, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this pin is tied to this
PCB plane. This plane should also reference all other
digital circuitry in the system.
3.9 Modulator Data Output Pin for
Channel 1 and Channel 0
(MDAT1/MDAT0)
MDAT0 and MDAT1 are the output pins for the
modulator serial bitstreams of ADC Channels 0 and 1,
respectively. These pins are high impedance when
their corresponding MODOUT bit is logic low. When the
MODOUT<1:0> is enabled, the modulator bit stream of
the corresponding channel is present on the pin and
updated at the AMCLK frequency (see Section 5.4
“Modulator Output Block” for a complete description
of the modulator outputs). These pins can be directly
connected to an MCU or a DSP when a specific digital
filtering is needed.
3.10 Data Ready Output (DR)
The data ready pin indicates that a new conversion
result is ready to be read. The default state of this pin
is high when DR_HIZ
= 1 and is high-impedance when
DR_HIZ
= 0 (Default). After each conversion is
finished, a logic-low pulse takes place on the data
ready pin to indicate that the conversion result is ready
as an interrupt. This pulse is synchronous with the
master clock and has a defined and constant width.
The data ready pin is independent of the SPI interface
and acts like an interrupt output. The data ready pin
state is not latched and the pulse width (and period) are
both determined by the MCLK frequency,
over-sampling rate and internal clock pre-scale
settings. The DR
pulse width is equal to one DMCLK
period, and the frequency of the pulses is equal to
DRCLK (see Figure 1-3).
Note: This pin should not be left floating when
DR_HIZ
bit is low; a 100 kΩ pull-up
resistor connected to DV
DD
is
recommended.