Datasheet

 2012-2013 Microchip Technology Inc. DS20002286B-page 19
MCP3911
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
3.1 Master Reset (RESET)
This pin is active-low and places the entire chip in a
Reset state when active.
When RESET
=D
GND
, all registers are reset to their
default value, no communication can take place and no
clock is distributed inside the part except in the input
structure, if MCLK is applied (if idle, no clock is
distributed). This state is equivalent to a POR state.
Since the default state of the ADCs is on, the analog
power consumption when RESET
=D
GND
is
equivalent to R
ESET =V
DD
. Only the digital power
consumption is largely reduced because this current
consumption is essentially dynamic and is reduced
drastically when there is no clock running.
All the analog biases are enabled during a Reset so
that the part is fully operational just after a RESET
rising edge, if the MCLK is applied during the rising
edge. If not applied, there is a small time after RESET
when the conversion may not be accurate,
corresponding to the startup of the charge pump of the
input structure.
This input is Schmitt-triggered.
3.2 Digital V
DD
(DV
DD
)
DV
DD
is the power supply pin for the digital circuitry
within the MCP3911. For specified operation, this pin
requires appropriate bypass capacitors and should be
maintained between 2.7V and 3.6V.
3.3 Analog V
DD
(AV
DD
)
AV
DD
is the power supply pin for the analog circuitry
within the MCP3911. For specified operation, this pin
requires appropriate bypass capacitors and should be
maintained between 2.7V and 3.6V.
TABLE 3-1: PIN FUNCTION TABLE
Pin No.
SSOP
Pin No.
QFN
Symbol Function
1 18 RESET
Master Reset Logic Input Pin
219 DV
DD
Digital Power Supply Pin
320 AV
DD
Analog Power Supply Pin
4 1 CH0+ Non-Inverting Analog Input Pin for Channel 0
5 2 CH0- Inverting Analog Input Pin for Channel 0
6 3 CH1- Inverting Analog Input Pin for Channel 1
7 4 CH1+ Non-Inverting Analog Input Pin for Channel 1
85 A
GND
Analog Ground Pin, Return Path for internal analog circuitry
9 6 REFIN+/OUT Non-Inverting Voltage Reference Input and Internal Reference Output Pin
10 7 REFIN- Inverting Voltage Reference Input Pin
11 8 D
GND
Digital Ground Pin, Return Path for internal digital circuitry
12 9 MDAT1 Modulator Data Output Pin for Channel 1
13 10 MDAT0 Modulator Data Output Pin for Channel 0
14 11 DR
Data Ready Signal Output Pin
15 12 OSC1/CLKI Oscillator Crystal Connection Pin or External Clock Input Pin
16 13 OSC2 Oscillator Crystal Connection Pin
17 14 CS
Serial Interface Chip Select Pin
18 15 SCK Serial Interface Clock Input Pin
19 16 SDO Serial Interface Data Input Pin
20 17 SDI Serial Interface Data Input Pin
— 21 EP Exposed Thermal Pad. Must be connected to A
GND
or left floating.