MCP3911 3.3V Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -106.5 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 111 dB SFDR for Each Channel • 2.7V – 3.6V AVDD, DVDD • Programmable Data Rate up to 125 ksps - 4 MHz Maximum Sampling Frequency • Oversampling Ratio up to 4096 • Ultra Low Power Shutdown Mode with <2 µA • -122 dB Crosstalk between the Two Channels • Low Drift 1.
MCP3911 Functional Block Diagram REFIN/OUT REFIN- DVDD AVDD Voltage Reference + - AMCLK VREFEXT VREF DMCLK/DRCLK VREF- VREF+ ANALOG CH0+ + CH0- PGA CH1+ + CH1- PGA DMCLK ' 6 Modulator + ) X Phase PHASE <11:0> Shifter OFFCAL_CH1 GAINCAL_CH1 <23:0> <23:0> DATA_CH1 <23:0> + MOD<7:4> OSR<2:0> PRE<1:0> OFFCAL_CH0 GAINCAL_CH0 <23:0> <23:0> DATA_CH0 <23:0> MOD<3:0> ' 6 Modulator Xtal Oscillator OSC1 MCLK OSC2 DIGITAL SINC3+ SINC1 DR SDO Digital SPI Interface X RESET SDI SCK CS
MCP3911 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS † VDD .............................................
MCP3911 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, AZ_FREQ = 0, DITHER<1:0> = 11, BOOST<1:0> = 10; VCM = 0V; TA = -40°C to +125°C; VIN = 1.2VPP = 424 mVRMS at 50/60 Hz on both channels.
MCP3911 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, AZ_FREQ = 0, DITHER<1:0> = 11, BOOST<1:0> = 10; VCM = 0V; TA = -40°C to +125°C; VIN = 1.2VPP = 424 mVRMS at 50/60 Hz on both channels. Characteristic Sym Min Typ Max Units Conditions VREF 1.176 1.2 1.
MCP3911 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, AZ_FREQ = 0, DITHER<1:0> = 11, BOOST<1:0> = 10; VCM = 0V; TA = -40°C to +125°C; VIN = 1.2VPP = 424 mVRMS at 50/60 Hz on both channels. Characteristic Sym Min Typ Max Units Conditions Operating Current, Digital IDD,D — 0.2 0.
MCP3911 TABLE 1-3: SERIAL AC CHARACTERISTICS TABLE Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, GAIN = 1, CLOAD = 30 pF.
MCP3911 CS fSCK tHI tCSH tLO Mode 1,1 SCK Mode 0,0 tDO tDIS tHO MSB out SDO LSB out DON’T CARE SDI FIGURE 1-1: Serial Output Timing Diagram. tCSD CS Mode 1,1 SCK Mode 0,0 tSU SDI tCSH tCLD tHD MSB in LSB in HI-Z SDO FIGURE 1-2: tCLE fSCK tHI tLO tCSS Serial Input Timing Diagram. 1/fD tDRP DR tDODR SCK SDO FIGURE 1-3: DS20002286B-page 8 Data Ready Pulse/Sampling Timing Diagram. 2012-2013 Microchip Technology Inc.
MCP3911 H Waveform for tDIS Timing Waveform for tDO SCK CS VIH tDO 90% SDO SDO tDIS HI-Z 10% Timing Waveform for MDAT0/1 Modulator Output Function OSC1/CLKI tDOMDAT MDAT FIGURE 1-4: Timing Diagrams (Continued). 2012-2013 Microchip Technology Inc.
MCP3911 NOTES: DS20002286B-page 10 2012-2013 Microchip Technology Inc.
MCP3911 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 3.
MCP3911 Frequency of Occurrence Frequency of Occurrence Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS at 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 15.3 15.4 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6 Effective Number of Bits (SINAD) 104.5 106 107.5 109 110.5 112 113.5 115 Spurious Free Dynamic Range (dBFS) FIGURE 2-10: Frequency of Occurrence 94.5 94.6 94.8 94.9 95.1 95.2 95.
MCP3911 120 110 100 90 80 70 60 50 40 30 20 10 0 Dithering = Maximum Dithering = Medium Dithering = Minimum Dithering = None 32 64 FIGURE 2-13: Total Harmonic Distortion (dBc) Signal-to-Noise and Distortion Ratio (dB) Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS at 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X.
MCP3911 Boost = 2x Boost = 1x Boost = 0.66x Boost = 0.5x 5 10 15 20 Frequency (MHz) 95 Auto Zero Speed = Fast 90 85 Auto Zero Speed = Slow 80 75 30 2 FIGURE 2-20: 4 8 Gain (V/V) 16 FIGURE 2-21: Off). DS20002286B-page 14 16 32 SINAD vs. GAIN (Dithering 4 8 Gain (V/V) 16 32 SINAD vs. GAIN vs. AZ Channel 1 Channel 0 -6 120 110 100 90 80 70 60 50 40 30 20 10 0 4 8 Gain (V/V) 2 -5 -4 -3 -2 -1 0 1 Input Signal Amplitude (dBFS) FIGURE 2-23: Amplitude. SINAD vs. GAIN.
MCP3911 Channel 1 Channel 0 -5 -4 -3 -2 -1 0 1 Input Signal Amplitude (dBFS) FIGURE 2-25: Amplitude. Spurious Free Dyanmic Range (dBFS) 90 80 70 60 50 G=1 G=2 G=4 G=8 G = 16 G = 32 40 30 20 10 0 -6 2 3 -50 -25 0 FIGURE 2-28: SNR vs. Input Signal 25 50 75 100 Temperature (°C) 125 150 SINAD vs. Temperature.
MCP3911 400 5 350 4 300 3 Gain Error (%) Channel 1 Offset (mV) Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS at 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 250 G=1 G=2 G=4 G=8 G = 16 G = 32 200 150 100 50 G=2 1 G=4 0 -1 G=8 -2 0 -3 -4 G = 32 G = 16 -5 -50 -25 0 FIGURE 2-31: Temperature. 25 50 75 100 Temperature (°C) 125 Channel 0 Offset vs.
MCP3911 Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS at 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 4.5 14 Frequency of Occurrence 4 12 IDD (mA) 10 8 6 3 2.5 2 AIDD, Boost = 1x AIDD, Boost = 0.6x 1.5 4 1 2 0.5 AIDD, Boost = 0.5x DIDD, All Boost Settings 0 0 0 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.
MCP3911 NOTES: DS20002286B-page 18 2012-2013 Microchip Technology Inc.
MCP3911 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin No. SSOP Pin No.
MCP3911 3.4 ADC Differential Analog inputs (CHn+/CHn-) The two fully differential analog voltage inputs for the Delta-Sigma ADCs are: • CH0 and CH0+ • CH1 and CH1+ The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mV/GAIN with VREF = 1.2V. The maximum differential voltage is proportional to the VREF voltage.
MCP3911 3.11 Oscillator and Master Clock Input Pins (OSC1/CLKI, OSC2) OSC1/CLKI and OSC2 provide the master clock (MCLK) for the device. When CLKEXT = 0, a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in Table 5-3 as a function of the BOOST and PGA settings chosen.
MCP3911 NOTES: DS20002286B-page 22 2012-2013 Microchip Technology Inc.
MCP3911 4.0 TERMINOLOGIES AND FORMULAS This section defines the terms and formulas used throughout this data sheet.
MCP3911 Since this is the output data rate and the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. TABLE 4-2: PRE <1:0> The following table describes the various combinations of OSR and PRESCALE and their associated AMCLK, DMCLK and DRCLK rates.
MCP3911 4.5 OSR – Oversampling Ratio 4.8 Integral Non-Linearity Error This is the ratio of the sampling frequency to the output data rate. OSR = DMCLK/DRCLK. The default OSR is 256 or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz, fD = 3.90625 ksps. The following bits in the CONFIG register are used to change the oversampling ratio (OSR).
MCP3911 4.11 Total Harmonic Distortion (THD) The total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by Equation 4-6. EQUATION 4-6: HarmonicsPower THD ( dB ) = 10 log ----------------------------------------------------- FundamentalPower The THD calculation includes the first 35 harmonics for the MCP3911 specifications. The THD is usually only measured with respect to the 10 first harmonics.
MCP3911 4.15 Dithering To suppress or attenuate the idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop to “decorrelate” the outputs and “break” the idle tones behavior. Usually, a random or pseudo-random generator adds an analog or digital error to the feedback loop of the Delta-Sigma ADC to ensure that no tonal behavior can happen at its outputs.
MCP3911 4.19 ADC Reset Mode 4.20 Hard Reset Mode (RESET = DGND) ADC Reset mode (also called Soft Reset mode) can only be entered through setting high the RESET<1:0> bits in the Configuration register. This mode is defined as the condition where the converters are active, but their output is forced to ‘0’. This mode is only available during a POR or when the RESET pin is pulled low. The RESET pin low state places the device in a Hard Reset mode.
MCP3911 When an ADC exits ADC Shutdown mode, any phase delay present before shutdown was entered is still present. If one ADC was not in Shutdown mode, the ADC exiting Shutdown mode automatically resynchronizes the phase delay relative to the other ADC channel, per the phase delay register block and give data ready pulses accordingly. When exiting full Shutdown mode, the device resets to its default configuration state.
MCP3911 NOTES: DS20002286B-page 30 2012-2013 Microchip Technology Inc.
MCP3911 5.0 DEVICE OVERVIEW 5.1 Analog Inputs (CHn+/-) The MCP3911 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 4.0 kV HBM and 300V MM contact charge. These structures allow bipolar ±2V continuous voltage with respect to AGND to be present at their inputs without the risk of permanent damage.
MCP3911 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT 5.3.3 The Delta-Sigma modulators include a programmable biasing circuit to further adjust the power consumption to the sampling speed applied through the MCLK. This can be programmed through the BOOST<1:0> bits, which are applied to both channels simultaneously. For a specified voltage reference value of 1.2V, the modulator’s specified differential input range is ±600 mV.
MCP3911 5.3.4 AUTOZEROING FREQUENCY SETTING (AZ_FREQ) The MCP3911 modulators include an auto-zeroing algorithm to improve the offset error performance and greatly diminish 1/f noise in the ADC. This algorithm allows the device to reach very high SNR and flattens the noise spectrum at the output of the ADC (see performance graphs Figure 2-1, Figure 2-2, Figure 2-3 and Figure 2-4). This auto-zeroing algorithm is performed synchronously with the MCLK coming to the device.
MCP3911 Since the Reset and Shutdown SPI commands are asynchronous, the MDAT pins are resynchronized with DMCLK after each time the part goes out of Reset and Shutdown. This means that the first output of MDAT, after a Soft Reset or a Shutdown, is always 0011 after the first DMCLK rising edge. The two MDAT output pins are in high-impedance if the RESET pin is low. COMP COMP COMP COMP <0> <1> <3> <2> AMCLK DMCLK 5.
MCP3911 The SINC1 filter following the SINC3 filter is only enabled for the high OSR settings. This SINC1 filter provides additional rejection at a low cost with little modification to the -3 dB bandwidth. For 24-Bit Output mode (WIDTH = 1), the output of the sinc filter is padded on the right with least significant zeros, up to 24 bits, for any resolution less than 24 bits.
MCP3911 5.6 ADC Output Coding Equation 5-3 is only true for DC inputs. For AC inputs, this transfer function needs to be multiplied by the transfer function of the SINC3+SINC1 filter (see Equation 5-1 and Equation 5-3). The second order modulator, SINC3+SINC1 filter, PGA, VREF and analog input structure, all work together to produce the device transfer function for the analog to digital conversion (see Equation 5-3).
MCP3911 TABLE 5-8: OSR = 32 OUTPUT CODE EXAMPLES ADC Output code (MSB First) 0 0 0 1 1 1 1 1 0 1 0 0 5.7 5.7.1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 Voltage Reference INTERNAL VOLTAGE REFERENCE The MCP3911 contains an internal voltage reference source specially designed to minimize drift overtemperature.
MCP3911 5.7.3 5.8 TEMPERATURE COMPENSATION (VREFCAL REGISTER) Power-on Reset The MCP3911 contains an internal POR circuit that monitors both analog and digital supply voltages during operation. The typical threshold for a power-up event detection is 2.1V ±5% and a typical start-up time (tPOR) of 50 µs. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.
MCP3911 5.9 RESET Effect On Delta-Sigma Modulator/SINC Filter When the RESET pin is logic low, both ADCs are in Reset mode and output code 0x0000h. The RESET pin performs a hard reset (DC biases still on, part ready to convert) and clears all charges contained in the DeltaSigma modulators. The comparator’s output is 0011 for each ADC. The SINC filters are all reset, as well as their double output buffers. This pin is independent of the serial interface. It brings all the registers to the default state.
MCP3911 TABLE 5-9: PHASE VALUES WITH MCLK = 4 MHZ, OSR = 4096 Phase Register Value Hex Delay (CH0 relative to CH1) 0 1 1 1 1 1 1 1 1 1 1 1 0x7FF + 2047 µs 0 1 1 1 1 1 1 1 1 1 1 0 0x7FE + 2046 µs 0 0 0 0 0 0 0 0 0 0 0 1 0x001 + 1 µs 0 0 0 0 0 0 0 0 0 0 0 0 0x000 0 µs 1 1 1 1 1 1 1 1 1 1 1 1 0xFFF - 1 µs 1 0 0 0 0 0 0 0 0 0 0 1 0x801 - 2047 µs 1 0 0 0 0 0 0 0 0 0 0 0 0x800 -2048 µs 5.
MCP3911 5.12.1 DIGITAL OFFSET ERROR CALIBRATION The OFFCAL_CHn registers are 23-bit plus sign two’s complement register, which LSB value is the same as the Channel ADC Data. These two registers are then added bit-by-bit to the ADC output codes, if the EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL bit does not create any pipeline delay, the offset addition is instantaneous. For low OSR values, only the significant digits are added to the output (up to the resolution of the ADC.
MCP3911 NOTES: DS20002286B-page 42 2012-2013 Microchip Technology Inc.
MCP3911 6.0 6.1 SERIAL INTERFACE DESCRIPTION A5 A4 A3 A2 A1 A0 Overview The MCP3911 device is compatible with SPI Modes 0,0 and 1,1. Data is clocked out of the MCP3911 on the falling edge of SCK and data is clocked into the MCP3911 on the rising edge of SCK. In these modes, SCK can Idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent.
MCP3911 6.5 SPI MODE 1,1 – Clock Idle High, Read/Write Examples In this SPI mode, SCK idles high. For the MCP3911, this means that there is a falling edge on SCK before there is a rising edge. Note: Changing from an SPI Mode 1,1 to an SPI Mode 0,0 is possible and can be done while CS pin is logic high.
MCP3911 6.6 SPI MODE 0,0 – Clock Idle Low, Read/Write Examples In this SPI mode, SCK idles low. For the MCP3911, this means that there is a rising edge on SCK before there is a falling edge.
MCP3911 6.7 Continuous Communication, Looping on Address Sets If the user wishes to read back one or both ADC channels continuously, the internal address counter of the MCP3911 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS pin returns logic high.
MCP3911 CS SCK CH0 ADC ADDR/R SDI SDO CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte HiZ CH1 ADC Lower byte CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte CH1 ADC Lower byte DR These bytes are not present when WIDTH=0 (16-bit mode) FIGURE 6-7: 6.7.2 Typical Continuous Read Communication (SPI Mode 1,1).
MCP3911 AVDD, DVDD CS SCK 00011010 11XXXXXX SDI CONFIG2 CONFIG2 00001110 xxxxxxxx PHASE ADDR/W xxxxxxxx PHASE xxxxxxxx GAIN xxxxxxxx xxxxxxxx xxxxxxxx STATUSCOM xxxxxxxx CONFIG ADDR/W Optional RESET of both ADCs FIGURE 6-8: 6.9 One command for writing complete configuration (without calibration) Recommended Configuration Sequence at Power-up.
MCP3911 6.10.1 DATA READY PIN (DR) CONTROL USING DRMODE BITS There are four modes that control the data ready pulses and these modes are set with the DRMODE<1:0> bits in the STATUSCOM register. For power metering applications, DRMODE<1:0> = 00 is recommended (Default mode).
MCP3911 Figure 6-9 represents the behavior of the data ready pin with the different DRMODE configurations while shutdown or reset is applied. DS20002286B-page 50 2012-2013 Microchip Technology Inc.
MCP3911 DS20002286B-page 51 3*DRCLK period 3*DRCLK period DRCLK Period 1 DMCLK Period Internal reset synchronisation (1 DMCLK period) DRCLK Period DRCLK period RESET RESET<0> or SHUTDOWN<0> RESET<1> or PHASE > 0 SHUTDOWN<1> DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D1
MCP3911 NOTES: DS20002286B-page 52 2012-2013 Microchip Technology Inc.
MCP3911 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below, followed by a detailed description of the registers. All registers are split in 8-bit long registers which can be addressed and read separately. Read and Write modes define the groups and types of registers for continuous read/write communication or looping on address sets as shown in Table 7-2.
MCP3911 REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES READ<1:0> = “10” 0x00 CHANNEL 0 0x01 CHANNEL 1 TYPE 0x02 0x03 0x04 0x05 MOD 0x06 PHASE 0x07 GAIN 0x09 0x0B 0x0C 0x0D 0x0E OFFCAL_CH0 0x0F 0x10 0x11 GAINCAL_CH0 OFFCAL_CH1 0x12 Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static NOT WRITABLE Static Static Static Static Static TYPE Static
MCP3911 7.1 CHANNEL Registers – ADC Channel Data Output Registers The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only and can be accessed independently or linked together (with READ<1:0> bits). These registers are latched when an ADC read communication occurs. When a data ready event occurs during a read communication, the most REGISTER 7-1: current ADC data is also latched to avoid data corruption issues.
MCP3911 7.2 MOD Register – Modulators Output Register The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on both ADCs. Each bit in this register corresponds to one comparator output on one of the channels. Name Bits Address Cof MOD 8 0x06 R/W Note: This register should not be written to maintain ADC accuracy.
MCP3911 7.3 PHASE Register – Phase Configuration Register Any write to one of these two addresses (0x07 and 0x08) creates an internal reset and restart sequence.
MCP3911 7.
MCP3911 7.
MCP3911 REGISTER 7-5: STATUSCOM REGISTER (CONTINUED) bit 5 WRITE: Address Loop Setting for Write mode 1 = Address counter loops on entire register map (DEFAULT) 0 = Address not incremented, continually write same single register bit 4-3 WIDTH<1:0> ADC Channel output data word width 11 = Both channels are in 24-bit mode(DEFAULT) 10 = Channel1 in 16-bit mode, Channel0 in 24-bit mode 01 = Channel1 in 16-bit mode, Channel0 in 24-bit mode 00 = Both channels are in 16-bit mode bit 2 EN_OFFCAL Enables or di
MCP3911 7.
MCP3911 REGISTER 7-6: CONFIG REGISTER (CONTINUED) bit 3 Not implemented: Read as ‘0’. bit 2 VREFEXT Internal Voltage Reference Shutdown Control 1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (Default) bit 1 CLKEXT Internal Clock selection bits 1 = External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power consumption) (Default) 0 = Crystal oscillator is enabled. A crystal must be placed between OSC1 and OSC2 pins.
MCP3911 7.8 GAINCAL_CHn Registers - Digital Gain Error Calibration Registers Name Bits Address Cof GAINCAL_CH0 24 0x11 R/W GAINCAL_CH1 24 0x17 R/W REGISTER 7-8: R/W-0 GAINCAL_CHn<23> GAINCAL_CHn REGISTER R/W-0 R/W-0 GAINGAINCAL_CHn<22> CAL_CHn<21> ... R/W-0 R/W-0 ...
MCP3911 NOTES: DS20002286B-page 64 2012-2013 Microchip Technology Inc.
MCP3911 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 20-Lead QFN (4x4x0.9 mm) PIN 1 Example: PIN 1 20-Lead SSOP 3911A0 e3 E/ML^^ 316256 Example: MCP3911A0 e3 E/SS^^ 1316256 Legend: XX...
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MCP3911 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2012-2013 Microchip Technology Inc.
MCP3911 NOTES: DS20002286B-page 70 2012-2013 Microchip Technology Inc.
MCP3911 APPENDIX A: REVISION HISTORY Revision B (October 2013) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Corrected ESD values in Absolute Maximum Ratings † section and throughout the document. Updated Section 3.0, Pin Description. Added new Section 6.10.2, ADC Channels latching and Synchronization. Updated Table 7-2. Added note to Section 7.2, MOD Register – Modulators Output Register. Minor grammatical and spelling corrections.
MCP3911 NOTES: DS20002286B-page 72 2012-2013 Microchip Technology Inc.
MCP3911 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X Device Address Options X Tape and Temperature Reel Range /XX Package Device: MCP3911A0: Two Channel Analog Font End Converter Address Options: XX A6 A5 A0* = 0 0 A1 = 0 1 A2 = 1 0 A3 = 1 1 * Default option.
MCP3911 NOTES: DS20002286B-page 74 2012-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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