Datasheet

MCP3221
DS20001732E-page 20  2002-2017 Microchip Technology Inc.
6.3 Device Polling
In some instances, it may be necessary to test for
MCP3221 presence on the I
2
C bus without performing
a conversion as described in Figure 6-4 where the R/W
bit in the address byte is set to a zero. The MCP3221
acknowledges by pulling SDA low during the ACK clock
and then release the bus back to the I
2
C master. A Stop
or repeated Start bit can be issued from the master and
I
2
C communication can continue.
FIGURE 6-4: Device Polling.
6.4 Device Power and Layout
Considerations
6.4.1 POWERING THE MCP3221
V
DD
supplies the power to the device and the reference
voltage. A bypass capacitor value of 0.1 µF is recom-
mended. Adding a 10 µF capacitor in parallel is recom-
mended to attenuate higher frequency noise that is
present in some systems.
FIGURE 6-5: Powering the MCP3221.
6.4.2 LAYOUT CONSIDERATIONS
When laying out a printed circuit board for use with
analog components, care should be taken to reduce
noise wherever possible. A bypass capacitor from V
DD
to ground must be used always with this device and
placed as close as possible to the device pin. A bypass
capacitor value of 0.1 µF is recommended.
Digital and analog traces should be separated as much
as possible on the board, with no traces running
underneath the device or the bypass capacitor. Extra
precautions should be taken to keep traces with high-
frequency signals (such as clock lines) as far as
possible from analog traces.
Use of an analog ground plane is recommended in
order to keep the ground potential the same for all
devices on the board. Providing V
DD
connections to
devices in a Star configuration can also reduce noise
by eliminating current return paths and associated
errors (Figure 6-6). For more information on layout tips
when using the MCP3221 or other ADC devices, refer
to the Microchip Technology Application Note, “AN688
Layout Tips for 12-Bit A/D Converter Application”
(DS00688).
FIGURE 6-6: V
DD
traces arranged in a
Star configuration in order to reduce errors
caused by current return paths.
Note: When power-down of the MCP3221 is
needed during applications (after power-
up), it is highly recommended to bring
down the V
DD
to V
SS
level. This can guar-
antee a Full Reset of the device for the
next power-up cycle.
123456789
SCL
SDA
1
00
1 A2 A1A0 0
ACK
Start
bit
Address Byte
Address bits
Device bits
R/W
Start
bit
MCP3221 response
V
DD
V
DD
AIN
SCL
SDA
To
Microcontroller
10 µF
MCP3221
0.1 µF
V
DD
R
PU
R
PU
V
DD
Connection
Device 1
Device 2
Device 3
Device 4