Datasheet

MCP3221
DS20001732E-page 14  2002-2017 Microchip Technology Inc.
4.0 DEVICE OPERATION
The MCP3221 employs a classic SAR architecture.
This architecture uses an internal sample and hold
capacitor to store the analog input while the conversion
is taking place. At the end of the acquisition time, the
input switch of the converter opens and the device uses
the collected charge on the internal sample and hold
capacitor to produce a serial 12-bit digital output code.
The acquisition time and conversion is self-timed using
an internal clock. After each conversion, the results are
stored in a 12-bit register that can be read at any time.
Communication with the device is accomplished with a
2-wire, I
2
C interface. Maximum sample rates of
22.3 ksps are possible with the MCP3221 in a continu-
ous-conversion mode and an SCL clock rate of
400 kHz.
4.1 Digital Output Code
The digital output code produced by the MCP3221 is a
function of the input signal and power supply voltage,
V
DD
. As the V
DD
level is reduced, the LSB size is
reduced accordingly. The theoretical LSB size is shown
below.
EQUATION
The output code of the MCP3221 is transmitted serially
with MSB first. The format of the code is straight binary.
4.2 Conversion Time (t
CONV
)
The conversion time is the time required to obtain the
digital result once the analog input is disconnected
from the holding capacitor. With the MCP3221, the
specified conversion time is typically 8.96 µs. This time
is dependent on the internal oscillator and is
independent of SCL.
4.3 Acquisition Time (t
ACQ
)
The acquisition time is the amount of time the sample
cap array is acquiring charge.
The acquisition time is, typically, 1.12 µs. This time is
dependent on the internal oscillator and independent of
SCL.
4.4 Sample Rate
Sample rate is the inverse of the maximum amount of
time that is required from the point of acquisition of the
first conversion to the point of acquisition of the second
conversion.
The sample rate can be measured either by single or
continuous conversions. A single conversion includes
a Start bit, Address byte, two data bytes and a Stop bit.
This sample rate is measured from one Start bit to the
next Start bit.
For continuous conversions (requested by the Master
by issuing an Acknowledge after a conversion), the
maximum sample rate is measured from conversion to
conversion or a total of 18 clocks (two data bytes and
two Acknowledge bits). Refer to Section 5.2 “Device
Addressing” for more information.
FIGURE 4-1: Transfer Function.
LSB SIZE
V
DD
4096
------------
=
V
DD
= Supply voltage
1111 1111 1111 (4095)
1111 1111 1110 (4094)
A
IN
0000 0000 0001 (1)
0000 0000 0011 (3)
Output Code
V
DD
-1.5 LSB
.5 LSB
1.5 LSB
V
DD
-2.5 LSB
2.5 LSB
0000 0000 0000 (0)
0000 0000 0010 (2)