Datasheet

ManualsBrandsMicrochip ManualsADC - Analog to DigitalA / D Converter IC 12bit I²C 22.3kSPS

 2002-2017 Microchip Technology Inc. DS20001732E-page 1

MCP3221

Features

• 12-bit Resolution

• ±1 LSB DNL, ±2 LSB INL maximum

• 250 µA Max Conversion Current

• 5 nA Typical Standby Current, 1 µA maximum

•I

C Compatible Serial Interface

- 100 kHz I

C Standard mode

- 400 kHz I

C Fast mode

• Up to 8 Devices on a Single 2-wire Bus

• 22.3 ksps in I

C Fast mode

• Single-Ended Analog Input Channel

• On-Chip Sample and Hold

• On-Chip Conversion Clock

• Single-Supply Specified Operation: 2.7V to 5.5V

• Temperature Range:

- Extended: -40°C to +125°C

• Small SOT-23-5 package

Applications

• Data Logging

• Multi-Zone Monitoring

• Handheld Portable Applications

• Battery-Powered Test Equipment

• Remote or Isolated Data Acquisition

General Description

Microchip’s MCP3221 is a successive approximation

A/D converter (ADC) with a 12-bit resolution. Available

in the SOT-23 package, this device provides one sin-

gle-ended input with very low-power consumption.

Based on an advanced CMOS technology, the

MCP3221 provides a low maximum conversion current

and standby current of 250 µA and 1 µA, respectively.

Low-current consumption, combined with the small

SOT-23 package, make this device ideal for battery-

powered and remote data acquisition applications.

Communication to the MCP3221 is performed using a

2-wire, I

C compatible interface. Standard (100 kHz)

and Fast (400 kHz) I

C modes are available with the

device. An on-chip conversion clock enables

independent timing for the I

C and conversion clocks.

The device is also addressable, allowing up to eight

devices on a single 2-wire bus.

The MCP3221 runs on a single-supply voltage that

operates over a broad range of 2.7V to 5.5V. This

device also provides excellent linearity of ±1 LSB

differential nonlinearity (DNL) and ±2 LSB integral

nonlinearity (INL), maximum.

Package Type

5-Pin SOT-23

SCL

MCP3221

SDA

Low-Power 12-Bit A/D Converter with I

C Interface

Summary of content (30 pages)

PAGE 1
MCP3221 Low-Power 12-Bit A/D Converter with I2C Interface Features General Description • • • • • Microchip’s MCP3221 is a successive approximation A/D converter (ADC) with a 12-bit resolution. Available in the SOT-23 package, this device provides one single-ended input with very low-power consumption. Based on an advanced CMOS technology, the MCP3221 provides a low maximum conversion current and standby current of 250 µA and 1 µA, respectively.
PAGE 2
MCP3221 Functional Block Diagram VDD VSS DAC AIN – Sample and Hold Comparator + 12-bit SAR Clock Control Logic I2C Interface SCL DS20001732E-page 2 SDA  2002-2017 Microchip Technology Inc.
PAGE 3
MCP3221 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD...........................................................................................................................................................................+7.0V Analog input pin w.r.t. VSS ..................................................................................................................-0.6V to VDD +0.6V SDA and SCL pins w.r.t. VSS ...........................................................................
PAGE 4
MCP3221 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameter Sym. Min. Typ. Max. Units CIN, COUT — — 10 pF TA = 25°C, f = 1 MHz; (Note 2) CB — — 400 pF SDA drive low, 0.4V Operating Voltage VDD 2.7 — 5.5 V Conversion Current IDD — 175 250 µA Standby Current IDDS — 0.
PAGE 5
MCP3221 TIMING SPECIFICATIONS Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C. Parameter Sym. Min. Typ. Max.
PAGE 6
MCP3221 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.
PAGE 7
MCP3221 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Positive INL INL (LSB) INL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. Negative INL -50 -25 0 25 50 75 100 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 125 Positive INL Negative INL -50 -25 0 Temperature (°C) INL vs. Temperature. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 FIGURE 2-10: (VDD = 2.7V).
PAGE 8
MCP3221 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0 1024 2048 3072 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 4096 1024 2048 FIGURE 2-16: DNL vs. Code (Representative Part, VDD = 2.7V). Positive DNL DNL (LSB) DNL (LSB) FIGURE 2-13: DNL vs. Code (Representative Part).
PAGE 9
MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 3 Offset Error (LSB) Gain Error (LSB) 2 VDD = 2.7V 1 0 -1 -2 VDD = 5V -3 -50 -25 0 25 50 75 100 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 VDD = 5V VDD = 2.7V -50 125 -25 0 Gain Error vs. Temperature. 100 90 80 70 60 50 40 30 20 10 0 FIGURE 2-22: Temperature. VDD = 5V SINAD (dB) SNR (dB) FIGURE 2-19: VDD = 2.
PAGE 10
MCP3221 12 11.95 11.9 11.85 11.8 11.75 11.7 11.65 11.6 11.55 11.5 12 11.5 ENOB (rms) VDD = 5V 10.5 10 9.5 9 2.5 3 3.5 FIGURE 2-25: SFDR (dB) VDD = 2.7V 11 100 90 80 70 60 50 40 30 20 10 0 4 VDD (V) 4.5 5 5.5 1 10 Input Frequency (kHz) FIGURE 2-28: ENOB vs. VDD. fSAMP = 5.6 ksps -10 VDD = 2.7V -30 -50 -70 -90 -110 -130 1 0 10 500 FIGURE 2-26: SFDR vs. Input Frequency.
PAGE 11
MCP3221 200 180 160 140 120 100 80 60 40 20 0 100 90 80 70 60 50 40 30 20 10 0 IDDA (µA) IDD (µA) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. VDD = 5V VDD = 2.7V 0 100 200 300 2 I C Clock Rate (kHz) FIGURE 2-31: Rate. 0 IDDA (µA) IDD (µA) VDD = 5V 150 VDD = 2.7V 50 0 -50 -25 0 25 50 75 100 100 125 VDD = 5V VDD = 2.
PAGE 12
MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 2.1 Test Circuits 1000 100 VDD = 5V IDDS (nA) 10 1 0.1 10 µF 0.01 2 k 0.001 0.0001 -50 -25 0 25 50 75 100 Analog Input Leakage (nA) FIGURE 2-37: Temperature. AIN 125 Temperature (°C) VIN VDDSDA MCP3221 VSS SCL VCM = 2.5V FIGURE 2-39: -25 2 k IDDS (Standby) vs. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 0.
PAGE 13
MCP3221 3.0 PIN FUNCTIONS Table 3-1 lists the function of the pins. TABLE 3-1: PIN FUNCTION TABLE Name 3.1 Function VDD +2.7V to 5.5V Power Supply VSS Ground AIN Analog Input SDA Serial Data In/Out SCL Serial Clock In VDD and VSS The VDD pin, with respect to VSS, provides power to the device as well as a voltage reference for the conversion process. Refer to Section 6.4 “Device Power and Layout Considerations” for tips on power and grounding. 3.
PAGE 14
MCP3221 4.0 DEVICE OPERATION 4.2 The MCP3221 employs a classic SAR architecture. This architecture uses an internal sample and hold capacitor to store the analog input while the conversion is taking place. At the end of the acquisition time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. The acquisition time and conversion is self-timed using an internal clock.
PAGE 15
MCP3221 4.5 Differential Non-Linearity (DNL) In the ideal A/D converter transfer function, each code has a uniform width. That is, the difference in analog input voltage is constant from one code transition point to the next. Differential nonlinearity (DNL) specifies the deviation of any code in the transfer function from an ideal code width of 1 LSB. The DNL is determined by subtracting the locations of successive code transition points after compensating for any gain and offset errors.
PAGE 16
MCP3221 5.0 SERIAL COMMUNICATIONS 5.1 I2C Bus Characteristics The following bus protocol are defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions are defined (refer to Figure 5-1). 5.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 5.1.
PAGE 17
MCP3221 Device Addressing 5.3 The address byte is the first byte received following the Start condition from the master device. The first part of the control byte consists of a 4-bit device code, which is set to 1001 for the MCP3221. The device code is followed by three address bits: A2, A1 and A0. The default address bits are 101. Contact the Microchip factory for additional address bit options.
PAGE 18
MCP3221 5.3.2 The input signal is initially sampled with the first falling edge of the clock following the transmission of a logic-high R/W bit. Additionally, with the rising edge of the SCL, the ADC transmits an Acknowledge bit (ACK = 0). The master must release the data bus during this clock pulse to allow the MCP3221 to pull the line low (refer to Figure 5-3).
PAGE 19
MCP3221 6.0 APPLICATIONS INFORMATION 6.1 Driving the Analog Input The MCP3221 has a single-ended analog input (AIN). For proper conversion results, the voltage at the AIN pin must be kept between VSS and VDD. If the converter has no offset error, gain error, INL or DNL errors, and the voltage level of AIN is equal to or less than VSS + 1/2 LSB, the resultant code is 000h. Additionally, if the voltage at AIN is equal to or greater than VDD - 1.5 LSB, the output code is FFFh.
PAGE 20
MCP3221 6.3 Device Polling 6.4.2 In some instances, it may be necessary to test for MCP3221 presence on the I2C bus without performing a conversion as described in Figure 6-4 where the R/W bit in the address byte is set to a zero. The MCP3221 acknowledges by pulling SDA low during the ACK clock and then release the bus back to the I2C master. A Stop or repeated Start bit can be issued from the master and I2C communication can continue.
PAGE 21
MCP3221 6.4.3 USING A REFERENCE FOR SUPPLY The MCP3221 uses VDD as power and also as a reference. In some applications, it may be necessary to use a stable reference to achieve the required accuracy. Figure 6-7 shows an example using the MCP1541 as a 4.096V, 2% reference. VDD 1 µF MCP1541 CL 4.096V Reference AIN VDD SCL MCP3221 SDA RPU To Microcontroller 0.1 µF VDD FIGURE 6-7: Stable Power and Reference Configuration.  2002-2017 Microchip Technology Inc.
PAGE 22
MCP3221 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 5-Pin SOT-23 3 2 1 4 Part Number 2 1 3 4 5 Address Option SOT-23 MCP3221A0T-E/OT 000 GE MCP3221A1T-E/OT 001 GH MCP3221A2T-E/OT 010 GB MCP3221A3T-E/OT 011 GC MCP3221A4T-E/OT 100 GD GA * MCP3221A5T-E/OT 101 MCP3221A6T-E/OT 110 GF MCP3221A7T-E/OT 111 GG * Default option. Contact Microchip Factory for other address options. Legend: XX...
PAGE 23
MCP3221 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p B p1 n D 1  c A  L  A1 INCHES* Units Dimension Limits A2 MIN MILLIMETERS NOM MAX MIN NOM MAX Pitch n p .038 0.95 Outside lead pitch (basic) p1 .075 1.90 Number of Pins Overall Height 5 5 A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .
PAGE 24
MCP3221 NOTES: DS20001732E-page 24  2002-2017 Microchip Technology Inc.
PAGE 25
MCP3221 APPENDIX A: REVISION HISTORY Revision E (January 2017) • Added a note to Section 6.4.1 “Powering the MCP3221”. • Fixed Section 7.1 “Package Marking Information” format to reflect the correct package marking as “1 2 3 4” instead of “1 10 10 10”. • Updated Temperature Specifiations table to remove information on Industrial Temperature Range Revision D (January 2013) • Added a note to each package outline drawing. Revision C (July 2006) • Updated Section 5.
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MCP3221 NOTES: DS20001732E-page 26  2002-2017 Microchip Technology Inc.
PAGE 27
MCP3221 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 28
MCP3221 NOTES: DS20001732E-page 28  2002-2017 Microchip Technology Inc.
PAGE 29
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 30
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