Datasheet

MCP3204/3208
DS21298E-page 18 © 2008 Microchip Technology Inc.
FIGURE 4-1: Analog Input Model.
FIGURE 4-2: Maximum Clock Frequency
vs. Input resistance (R
S
) to maintain less than a
0.1 LSB deviation in INL from nominal
conditions.
C
PIN
VA
R
SS
CHx
7pF
V
T
= 0.6V
V
T
= 0.6V
I
LEAKEAGE
Sampling
Switch
SS
R
S
= 1 kΩ
C
SAMPLE
= DAC capacitance
V
SS
V
DD
= 20 pF
±1 nA
Legend
VA
=
Signal Source
I
leakage
=
Leakage Current At The Pin
Due To Various Junctions
R
ss
=
Source Impedance SS
=
Sampling switch
CHx
=
Input Channel Pad
R
s
=
Sampling switch resistor
C
pin
=
Input Pin Capacitance
C
sample
=
Sample/hold capacitance
V
t
=
Threshold Voltage
0.0
0.5
1.0
1.5
2.0
2.5
100 1000 10000
Input Resistance (Ohms)
Clock Frequency (MHz)
V
DD
= 5 V
V
DD
= 2.7 V