MCP2515 Stand-Alone CAN Controller with SPI Interface Features Description • Implements CAN V2.
MCP2515 NOTES: DS20001801J-page 2 2003-2019 Microchip Technology Inc.
MCP2515 1.0 DEVICE OVERVIEW 1.2 The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. The MCP2515 is a stand-alone CAN controller developed to simplify applications that require interfacing with a CAN bus. A simple block diagram of the MCP2515 is shown in Figure 1-1. The device consists of three main blocks: 1. 2. 3. 1.1 Interrupt pins are provided to allow greater system flexibility.
MCP2515 FIGURE 1-2: EXAMPLE SYSTEM IMPLEMENTATION Node Controller Node Controller Node Controller SPI SPI SPI MCP2515 MCP2515 MCP2515 TX TX TX RX XCVR RX RX XCVR XCVR CANH CANL TABLE 1-1: Name PINOUT DESCRIPTION PDIP/ SOIC Pin # TSSOP QFN I/O/P Pin # Pin # Type Description Alternate Pin Function TXCAN 1 1 19 O Transmit output pin to CAN bus — RXCAN 2 2 20 I Receive input pin from CAN bus — CLKOUT 3 3 1 O Clock output pin with programmable prescaler TX0RTS 4 4
MCP2515 1.4 Transmit/Receive Buffers/Masks/ Filters The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. Figure 1-3 shows a block diagram of these buffers and their connection to the protocol engine.
MCP2515 1.5 CAN Protocol Engine 1.5.3 The CAN protocol engine combines several functional blocks, shown in Figure 1-4 and described below. 1.5.1 PROTOCOL FINITE STATE MACHINE The heart of the engine is the Finite State Machine (FSM). The FSM is a sequencer that controls the sequential data stream between the TX/RX Shift register, the CRC register and the bus line. The FSM also controls the Error Management Logic (EML) and the parallel data stream between the TX/RX Shift registers and the buffers.
MCP2515 2.0 CAN MESSAGE FRAMES The MCP2515 supports standard data frames, extended data frames and remote frames (standard and extended), as defined in the CAN 2.0B specification. 2.1 Standard Data Frame The CAN standard data frame is shown in Figure 2-1. As with all other frames, the frame begins with a Startof-Frame (SOF) bit, which is of the dominant state and allows hard synchronization of all nodes.
MCP2515 2.4.1 ACTIVE ERRORS If an error-active node detects a bus error, the node interrupts transmission of the current message by generating an active error flag. The active error flag is composed of six consecutive dominant bits. This bit sequence actively violates the bit-stuffing rule. All other stations recognize the resulting bit-stuffing error, and in turn, generate error frames themselves, called error echo flags.
Start-of-Frame ID 10 0 Stored in Buffers Message Filtering Identifier 11 12 Arbitration Field ID3 2003-2019 Microchip Technology Inc.
Start-of-Frame ID10 0 ID3 Message Filtering Identifier 11 Stored in Buffers 11 18 Extended Identifier Arbitration Field ID0 SRR IDE EID17 000 Bit-Stuffing 8 Stored in Transmit/Receive Buffers Data Length Code 4 8N (0 N 8) Data Field 8 Data Frame (number of bits = 64 + 8N) 6 Control Field EID0 RTR RB1 RB0 DLC3 DS20001801J-page 10 Reserved Bits CRC 15 16 CRC Field IFS 11111111111 CRC Del Ack Slot Bit ACK Del 1 End-ofFrame 7 FIGURE 2-2: DLC0 32 MCP2515 EXTENDED DATA FRAME
ID3 Message Filtering Identifier 11 ID0 SRR IDE EID17 18 Extended Identifier Remote Frame with Extended Identifier Start-of-Frame ID10 0 11 32 100 Data Length Code 4 6 Control Field EID0 RTR RB1 RB0 DLC3 Reserved Bits 2003-2019 Microchip Technology Inc.
Start-of-Frame ID 10 0 Message Filtering Identifier 11 ID3 12 Arbitration Field 6 Control Field 4 0 0 0 Bit-Stuffing Data Length Code ID0 RTR IDE RB0 DLC3 DS20001801J-page 12 Reserved Bit 8 Data Frame or Remote Frame 8N (0 N 8) Data Field 8 Inter-Frame Space or Overload Frame 0 0 1 1 1 1 1 1 1 1 0 Error Delimiter Echo Error Flag Error Flag 0 0 0 0 0 0 0 8 £6 6 Error Frame FIGURE 2-4: DLC0 Interrupted Data Frame MCP2515 ACTIVE ERROR FRAME 2003-2019 Microchip Technology Inc.
2003-2019 Microchip Technology Inc.
MCP2515 NOTES: DS20001801J-page 14 2003-2019 Microchip Technology Inc.
MCP2515 3.0 MESSAGE TRANSMISSION 3.3 3.1 Transmit Buffers In order to initiate message transmission, the TXREQ bit (TXBnCTRL[3]) must be set for each buffer to be transmitted. This can be accomplished by: The MCP2515 implements three transmit buffers. Each of these buffers occupies 14 bytes of SRAM and are mapped into the device memory map. The first byte, TXBnCTRL, is a control register associated with the message buffer.
MCP2515 3.5 TXnRTS Pins 3.6 Aborting Transmission The TXnRTS pins are input pins that can be configured as: The MCU can request to abort a message in a specific message buffer by clearing the associated TXREQ bit. • Request-to-Send inputs, which provide an alternative means of initiating the transmission of a message from any of the transmit buffers • Standard digital inputs In addition, all pending messages can be requested to be aborted by setting the ABAT bit (CANCTRL[4]).
MCP2515 FIGURE 3-1: TRANSMIT MESSAGE FLOWCHART Start No The message transmission sequence begins when the device determines that the TXREQ bit (TXBnCTRL[3]) for any of the transmit registers has been set. Are any TXREQ (TXBnCTRL[3]) bits = 1? Yes Clearing the TXREQ bit while it is set, or setting the ABAT bit (CANCTRL[4]) before the message has started transmission, will abort the message.
MCP2515 REGISTER 3-1: TXBnCTRL: TRANSMIT BUFFER n CONTROL REGISTER (ADDRESS: 30h, 40h, 50h) U-0 R-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0 — ABTF MLOA TXERR TXREQ — TXP1 TXP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 ABTF: Message Aborted Flag bit 1 = Message was aborted 0 = Message completed transmission successfully bit 5 ML
MCP2515 REGISTER 3-2: TXRTSCTRL: TXnRTS PIN CONTROL AND STATUS REGISTER (ADDRESS: 0Dh) U-0 U-0 R-x R-x R-x R/W-0 R/W-0 R/W-0 — — B2RTS B1RTS B0RTS B2RTSM B1RTSM B0RTSM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 B2RTS: TX2RTS Pin State bit - Reads state of TX2RTS pin when in Digital Input mode - Reads as ‘0’ when pin is
MCP2515 REGISTER 3-3: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTER HIGH (ADDRESS: 31h, 41h, 51h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SID[10:3]: Standard Identifier bits REGISTER 3-4: TXBnSIDL: TRANSMIT BUFFER n STANDARD IDENTIFIER REGISTER LOW (
MCP2515 REGISTER 3-5: TXBnEID8: TRANSMIT BUFFER n EXTENDED IDENTIFIER 8 REGISTER HIGH (ADDRESS: 33h, 43h, 53h) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EID[15:8]: Extended Identifier bits REGISTER 3-6: TXBnEID0: TRANSMIT BUFFER n EXTENDED IDENTIFIER 0 REGIS
MCP2515 REGISTER 3-7: U-0 TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTER (ADDRESS: 35h, 45h, 55h) R/W-x — RTR U-0 U-0 — — R/W-x R/W-x (1) DLC3 DLC2 (1) R/W-x (1) DLC1 R/W-x DLC0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RTR: Remote Transmission Request bit 1 = Transmitted message will be a remote transmit reques
MCP2515 4.0 MESSAGE RECEPTION 4.1 Receive Message Buffering The MCP2515 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB) that acts as a third receive buffer (see Figure 4-2). 4.1.1 MESSAGE ASSEMBLY BUFFER Of the three receive buffers, the MAB is always committed to receiving the next message from the bus. The MAB assembles all messages received.
MCP2515 4.3 Start-of-Frame Signal 4.4.1 The RXnBF pins can be disabled to the high-impedance state by clearing the BnBFE bits (BFPCTRL[3:2]). If enabled, the Start-of-Frame signal is generated on the SOF pin at the beginning of each CAN message detected on the RXCAN pin. 4.4.2 The RXCAN pin monitors an Idle bus for a recessiveto-dominant edge. If the dominant condition remains until the sample point, the MCP2515 interprets this as a SOF and a SOF pulse is generated.
MCP2515 4.4.3 CONFIGURED AS DIGITAL OUTPUT When used as digital outputs, the BnBFM bits (BFPCTRL[1:0]) must be cleared and the BnBFE bits (BFPCTRL[3:2]) must be set for the associated buffer. In this mode, the state of the pin is controlled by the BnBFS bits (BFPCTRL[5:4]). Writing a ‘1’ to a BnBFS bit will cause a high level to be driven on the associated buffer full pin, while a ‘0’ will cause the pin to drive low.
MCP2515 FIGURE 4-3: RECEIVE FLOWCHART Start Detect Start of Message? No Yes Begin Loading Message into Message Assembly Buffer (MAB) Generate Error Frame Valid Message Received? No Yes Meets a Filter Criteria for RXB0? Yes No Meets a Filter Criteria for RXB1? Yes No Go to Start Determines if the Receive register is empty and able to accept a new message. Determines if RXB0 can roll over into RXB1 if it is full.
MCP2515 REGISTER 4-1: RXB0CTRL: RECEIVE BUFFER 0 CONTROL REGISTER (ADDRESS: 60h) U-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R-0 R-0 — RXM1 RXM0 — RXRTR BUKT BUKT1 FILHIT0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 RXM[1:0]: Receive Buffer Operating mode bits 11 = Turns mask/filters off; receives any message 10 = Reserved 01 = Re
MCP2515 REGISTER 4-2: RXB1CTRL: RECEIVE BUFFER 1 CONTROL REGISTER (ADDRESS: 70h) U-0 R/W-0 R/W-0 U-0 R-0 R-0 R-0 R-0 — RXM1 RXM0 — RXRTR FILHIT2 FILHIT1 FILHIT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-5 RXM[1:0]: Receive Buffer Operating mode bits 11 = Turns mask/filters off; receives any message 10 = Reserved 01 = Re
MCP2515 REGISTER 4-3: BFPCTRL: RXnBF PIN CONTROL AND STATUS REGISTER (ADDRESS: 0Ch) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — B1BFS B0BFS B1BFE B0BFE B1BFM B0BFM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 B1BFS: RX1BF Pin State bit (Digital Output mode only) - Reads as ‘0’ when RX1BF is configured as an interrupt
MCP2515 REGISTER 4-4: RXBnSIDH: RECEIVE BUFFER n STANDARD IDENTIFIER REGISTER HIGH (ADDRESS: 61h, 71h) R-x R-x R-x R-x R-x R-x R-x R-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SID[10:3]: Standard Identifier bits These bits contain the eight Most Significant bits of the Standard Identifier for the received messa
MCP2515 REGISTER 4-6: RXBnEID8: RECEIVE BUFFER n EXTENDED IDENTIFIER REGISTER HIGH (ADDRESS: 63h, 73h) R-x R-x R-x R-x R-x R-x R-x R-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EID[15:8]: Extended Identifier bits These bits hold bits 15 through 8 of the Extended Identifier for the received message REGISTER
MCP2515 REGISTER 4-8: RXBnDLC: RECEIVE BUFFER n DATA LENGTH CODE REGISTER (ADDRESS: 65h, 75h) U-0 R-x R-x R-x R-x R-x R-x R-x — RTR RB1 RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 RTR: Extended Frame Remote Transmission Request bit (valid only when IDE (RXBnSIDL[3]) = 1) 1 = Extended frame Remote T
MCP2515 4.5 Message Acceptance Filters and Masks The message acceptance filters and masks are used to determine if a message in the Message Assembly Buffer should be loaded into either of the receive buffers (see Figure 4-5). Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values. If there is a match, that message will be loaded into the appropriate receive buffer.
MCP2515 4.5.3 FILHIT BITS If the BUKT bit is clear, there are six codes corresponding to the six filters. If the BUKT bit is set, there are six codes corresponding to the six filters, plus two additional codes corresponding to the RXF0 and RXF1 filters that roll over into RXB1. Filter matches on received messages can be determined by the FILHIT bits in the associated RXBnCTRL register; FILHIT0 (RXB0CTRL[0]) for Buffer 0 and FILHIT[2:0] (RXB1CTRL[2:0]) for Buffer 1. 4.5.
MCP2515 REGISTER 4-10: RXFnSIDH: FILTER n STANDARD IDENTIFIER REGISTER HIGH (ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h)(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID[10:3]: Standard Identifier Filter bits These bits hold the filter bits to be applied to bit
MCP2515 REGISTER 4-12: RXFnEID8: FILTER n EXTENDED IDENTIFIER REGISTER HIGH (ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID[15:8]: Extended Identifier bits These bits hold the filter bits to be applied to bits[
MCP2515 REGISTER 4-14: RXMnSIDH: MASK n STANDARD IDENTIFIER REGISTER HIGH (ADDRESS: 20h, 24h)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown SID[10:3]: Standard Identifier Mask bits These bits hold the mask bits to be applied to bits[10:3] of the Standard Id
MCP2515 \ REGISTER 4-16: RXMnEID8: MASK n EXTENDED IDENTIFIER REGISTER HIGH (ADDRESS: 22h, 26h)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: x = Bit is unknown EID[15:8]: Extended Identifier bits These bits hold the filter bits to be applied to bits[15:8] of the Extend
MCP2515 5.0 BIT TIMING 5.1 All nodes on a given CAN bus must have the same Nominal Bit Rate (NBR). The CAN protocol uses NonReturn-to-Zero (NRZ) coding, which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitter’s clock.
MCP2515 5.2.2 PROPAGATION SEGMENT The Propagation Segment (PropSeg) exists to compensate for physical delays between nodes. The propagation delay is defined as twice the sum of the signal’s propagation time on the bus line, including the delays associated with the bus driver. The PropSeg is programmable from 1-8 TQs. 5.2.3 PHASE SEGMENT 1 (PS1) AND PHASE SEGMENT 2 (PS2) The two Phase Segments, PS1 and PS2, are used to compensate for edge phase errors on the bus.
MCP2515 5.4 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. Synchronization is the process by which the DPLL function is implemented. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (SyncSeg). The circuit will then adjust the values of PS1 and PS2 as necessary.
MCP2515 FIGURE 5-3: SYNCHRONIZING THE BIT TIME Input Signal (e = 0) SyncSeg PropSeg PhaseSeg2 (PS2) PhaseSeg1 (PS1) SJW (PS2) SJW (PS1) Sample Point Nominal Bit Time (NBT) No Resynchronization (e = 0) Input Signal (e > 0) SyncSeg PropSeg PhaseSeg2 (PS2) PhaseSeg1 (PS1) SJW (PS2) SJW (PS1) Sample Point Nominal Bit Time (NBT) Actual Bit Time Resynchronization to a Slower Transmitter (e > 0) Input Signal (e < 0) SyncSeg PropSeg PhaseSeg1 (PS1) SJW (PS1) PhaseSeg2 (PS2) SJW (PS2) Sample Poi
MCP2515 5.5 Programming Time Segments Some requirements for programming of the Time Segments: • PropSeg + PS1 PS2 • PropSeg + PS1 TDELAY • PS2 > SJW For example, assuming that a 125 kHz CAN baud rate with FOSC = 20 MHz is desired: TOSC = 50 ns, choose BRP[5:0] = 04h, then TQ = 500 ns. To obtain 125 kHz, the bit time must be 16 TQs. Typically, the sampling of the bit should take place at about 60-70% of the bit time, depending on the system parameters. Also, typically, the TDELAY is 1-2 TQs.
MCP2515 REGISTER 5-1: CNF1: CONFIGURATION REGISTER 1 (ADDRESS: 2Ah) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 SJW[1:0]: Synchronization Jump Width Length bits 11 = Length = 4 x TQ 10 = Length = 3 x TQ 01 = Length = 2 x TQ 00 = Length = 1 x TQ bit 5-0 BRP[5:0]: Baud Rate Prescaler bit
MCP2515 REGISTER 5-3: CNF3: CONFIGURATION REGISTER 3 (ADDRESS: 28h) R/W-0 R/W-0 U-0 U-0 U-0 SOF WAKFIL — — — R/W-0 R/W-0 R/W-0 PHSEG2[2:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SOF: Start-of-Frame signal bit If CLKEN (CANCTRL[2]) = 1: 1 = CLKOUT pin is enabled for SOF signal 0 = CLKOUT pin is enabled for clock out function If CLKEN (CANCTRL[2]) = 0: Bit is don’t care.
MCP2515 NOTES: DS20001801J-page 46 2003-2019 Microchip Technology Inc.
MCP2515 6.0 ERROR DETECTION The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. 6.1 CRC Error With the Cyclic Redundancy Check (CRC), the transmitter calculates special check bits for the bit sequence from the Start-of-Frame until the end of the data field. This CRC sequence is transmitted in the CRC field. The receiving node also calculates the CRC sequence using the same formula and performs a comparison to the received sequence.
MCP2515 FIGURE 6-1: ERROR MODES STATE DIAGRAM Reset REC < 127 or TEC < 127 Error-Active 128 Occurrences of 11 Consecutive “Recessive” Bits REC > 127 or TEC > 127 Error-Passive TEC > 255 Bus-Off DS20001801J-page 48 2003-2019 Microchip Technology Inc.
MCP2515 REGISTER 6-1: TEC: TRANSMIT ERROR COUNTER REGISTER (ADDRESS: 1Ch) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown TEC[7:0]: Transmit Error Count bits REGISTER 6-2: REC: RECEIVE ERROR COUNTER REGISTER (ADDRESS: 1Dh) R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4
MCP2515 REGISTER 6-3: EFLG: ERROR FLAG REGISTER (ADDRESS: 2Dh) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 RX1OVR RX0OVR TXBO TXEP RXEP TXWAR RXWAR EWARN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RX1OVR: Receive Buffer 1 Overflow Flag bit - Sets when a valid message is received for RXB1 and RX1IF (CANINTF[1]) = 1 - Must be reset by MCU bit 6 RX0OVR: Receive Bu
MCP2515 7.0 INTERRUPTS 7.2 Transmit Interrupt The MCP2515 has eight sources of interrupts. The CANINTE register contains the individual interrupt enable bits for each interrupt source. The CANINTF register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt can not be cleared if the respective condition still prevails.
MCP2515 7.6.1 RECEIVER OVERFLOW An overflow condition occurs when the MAB has assembled a valid receive message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated RXnOVR bit (EFLG) will be set to indicate the overflow condition. This bit must be cleared by the MCU. 7.6.2 RECEIVER WARNING The REC has reached the MCU warning limit of 96. 7.6.
MCP2515 REGISTER 7-1: CANINTE: CAN INTERRUPT ENABLE REGISTER (ADDRESS: 2Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MERRE WAKIE ERRIE TX2IE TX1IE TX0IE RX1IE RX0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MERRE: Message Error Interrupt Enable bit 1 = Interrupt on error during message reception or transmission 0 = Disabled bit 6 WAKIE: Wake-up Interrupt Enable bit
MCP2515 REGISTER 7-2: CANINTF: CAN INTERRUPT FLAG REGISTER (ADDRESS: 2Ch) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MERRF WAKIF ERRIF TX2IF TX1IF TX0IF RX1IF RX0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MERRF: Message Error Interrupt Flag bit 1 = Interrupt is pending (must be cleared by MCU to reset the interrupt condition) 0 = No interrupt is p
MCP2515 8.0 OSCILLATOR 8.2 The CLKOUT pin is provided to the system designer for use as the main system clock or as a clock input for other devices in the system. The CLKOUT has an internal prescaler which can divide FOSC by 1, 2, 4 and 8. The CLKOUT function is enabled and the prescaler is selected via the CANCTRL register (see Register 10-1). The MCP2515 is designed to operate with a crystal or ceramic resonator connected to the OSC1 and OSC2 pins.
MCP2515 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT(1) FIGURE 8-3: 330 k 330 k 74AS04 74AS04 To Other Devices MCP2510 74AS04 OSC1 0.1 mF XTAL Note 1: TABLE 8-1: Duty cycle restrictions must be observed (see Table 13-2). CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq. OSC1 OSC2 8.0 MHz 27 pF 27 pF 16.
MCP2515 9.0 RESET Both of these Resets are functionally equivalent. It is important to provide one of these two Resets after power-up to ensure that the logic and registers are in their default state. A hardware Reset can be achieved automatically by placing an RC on the RESET pin (see Figure 9-1). The values must be such that the device is held in Reset for a minimum of 2 μs after VDD reaches the operating voltage, as indicated in the electrical specification (tRL).
MCP2515 NOTES: DS20001801J-page 58 2003-2019 Microchip Technology Inc.
MCP2515 10.0 MODES OF OPERATION The MCP2515 has five modes of operation. These modes are: 1. 2. 3. 4. 5. Configuration mode Normal mode Sleep mode Listen-Only mode Loopback mode The operational mode is selected via the REQOP[2:0] bits (CANCTRL[7:5]); see Register 10-1). When changing modes, the mode will not actually change until all pending message transmissions are complete. The requested mode must be verified by reading the OPMODE[2:0] bits (CANSTAT[7:5]); see Register 10-2. 10.
MCP2515 10.4 Loopback Mode The filters and masks can be used to allow only particular messages to be loaded into the Receive registers. The masks can be set to all zeros to provide a mode that accepts all messages. The Loopback mode is activated by setting the Request Operation Mode bits in the CANCTRL register. Loopback mode will allow internal transmission of messages from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus.
MCP2515 REGISTER 10-2: CANSTAT: CAN STATUS REGISTER (ADDRESS: XEh) R-1 R-0 R-0 U-0 R-0 R-0 R-0 U-0 OPMOD2 OPMOD1 OPMOD0 — ICOD2 ICOD1 ICOD0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 x = Bit is unknown OPMOD[2:0]: Operation Mode bits 000 = Device is in Normal Operation mode 001 = Device is in Sleep mode 010 = Device is in Loopback mode 011 = Device is in Listen-Only mod
MCP2515 NOTES: DS20001801J-page 62 2003-2019 Microchip Technology Inc.
MCP2515 11.0 REGISTER MAP reading and writing of data. Some specific control and status registers allow individual bit modification using the SPI BIT MODIFY command. The registers that allow this command are shown as shaded locations in Table 11-1. A summary of the MCP2515 control registers is shown in Table 11-2. The register map for the MCP2515 is shown in Table 11-1. Address locations for each register are determined by using the column (higher order four bits) and row (lower order four bits) values.
MCP2515 NOTES: DS20001801J-page 64 2003-2019 Microchip Technology Inc.
MCP2515 12.0 SPI INTERFACE 12.4 12.1 Overview The READ RX BUFFER instruction (Figure 12-3) provides a means to quickly address a receive buffer for reading. This instruction reduces the SPI overhead by one byte, the address byte. The command byte actually has four possible values that determine the Address Pointer location. Once the command byte is sent, the controller clocks out the data at the address location, the same as the READ instruction (i.e., sequential reads are possible).
MCP2515 12.8 READ STATUS Instruction The READ STATUS instruction allows single instruction access to some of the often used status bits for message reception and transmission. The MCP2515 is selected by lowering the CS pin and the READ STATUS command byte, shown in Figure 12-8, is sent to the MCP2515. Once the command byte is sent, the MCP2515 will return eight bits of data that contain the status.
MCP2515 TABLE 12-1: SPI INSTRUCTION SET Instruction Name Instruction Format Description 1100 0000 Resets internal registers to the default state, sets Configuration mode. READ 0000 0011 Reads data from the register beginning at selected address. READ RX BUFFER 1001 0nm0 When reading a receive buffer, reduces the overhead of a normal READ command by placing the Address Pointer at one of four locations, as indicated by ‘n,m’.
MCP2515 FIGURE 12-2: READ INSTRUCTION CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction SI 0 0 0 0 0 Address Byte 0 1 A7 1 6 5 3 4 2 1 A0 Don’t Care Data Out High-Impedance 7 SO FIGURE 12-3: 5 n m 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction 1 4 3 2 1 0 READ RX BUFFER INSTRUCTION CS SI 6 0 0 1 0 n m Data Out High-Impedance SO FIGURE 12-4: Don’t Care 0 7 6 5 4 3 2 1 0 Address Points to Address
MCP2515 FIGURE 12-5: LOAD TX BUFFER INSTRUCTION a b c CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 1 0 0 Data In a 0 b c 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 12-6: Address Points to Addr 0 0 0 TX Buffer 0, Start at TXB0SIDH 0x31 0 0 1 TX Buffer 0, Start at TXB0D0 0x36 0 1 0 TX Buffer 1, Start at TXB1SIDH 0x41 0 1 1 TX Buffer 1, Start at TXB1D0 0x46 1 0 0 TX Buffer 2, Start at TXB2SIDH 0x51 1 0 1 TX Buffer 2, Start at TXB2D0 0x56 REQUEST-TO-S
MCP2515 FIGURE 12-8: READ STATUS INSTRUCTION CS 0 1 2 3 4 5 6 7 0 0 0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction 1 SI 0 1 0 0 Don’t Care SO Repeat Data Out Data Out High-Impedance 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 RX0IF (CANINTF[0]) RX1IF (CANINTF[1]) TXREQ (TXB0CNTRL[3]) TX0IF (CANINTF[2]) TXREQ (TXB1CNTRL[3]) TX1IF (CANINTF[3]) TXREQ (TXB2CNTRL[3]) TX2IF (CANINTF[4]) FIGURE 12-9: RX STATUS INSTRUCTION CS 0 1 2 3 4 5 6 7 0 0 0 8 9
MCP2515 FIGURE 12-10: SPI INPUT TIMING 3 CS 11 Mode 1,1 6 1 7 10 2 SCK Mode 0,0 4 SI 5 MSB In LSB In High-Impedance SO FIGURE 12-11: SPI OUTPUT TIMING CS 8 9 2 Mode 1,1 SCK Mode 0,0 12 SO 14 13 MSB Out LSB Out Don’t Care SI 2003-2019 Microchip Technology Inc.
MCP2515 NOTES: DS20001801J-page 72 2003-2019 Microchip Technology Inc.
MCP2515 13.0 ELECTRICAL CHARACTERISTICS 13.1 Absolute Maximum Ratings† VDD.............................................................................................................................................................................7.0V All Inputs and Outputs w.r.t. VSS ....................................................................................................... -0.6V to VDD + 1.0V Storage Temperature ..............................................................................
MCP2515 TABLE 13-1: DC CHARACTERISTICS DC Characteristics Param. No. Sym VDD = 2.7V to 5.5V Characteristic Min Max Industrial (I): TAMB = -40°C to +85°C Extended (E): TAMB = -40°C to +125°C Units Conditions VDD Supply Voltage 2.7 5.5 V VRET Register Retention Voltage 2.4 — V 2 VDD + 1 V SCK, CS, SI, TXnRTS Pins 0.7 VDD VDD + 1 V OSC1 Pin 0.85 VDD VDD V RESET Pin 0.85 VDD VDD V RXCAN, TXnRTS Pins -0.3 0.15 * VDD V SCK, CS, SI Pins -0.3 0.4 * VDD V OSC1 Pin VSS 0.
MCP2515 TABLE 13-2: OSCILLATOR TIMING CHARACTERISTICS Oscillator Timing Characteristics(1) Param. No. Note 1: Sym Characteristic Min Max Units Conditions Clock In Frequency 1 1 40 25 MHz MHz VDD = 4.5V to 5.5V VDD = 2.7V to 5.5V TOSC Clock In Period 25 40 1000 1000 ns ns VDD = 4.5V to 5.5V VDD = 2.7V to 5.5V TDUTY Duty Cycle (external clock input) 0.45 0.55 — TOSH/(TOSH + TOSL) This parameter is periodically sampled and not 100% tested.
MCP2515 TABLE 13-5: CLKOUT PIN AC CHARACTERISTICS CLKOUT Pin AC/DC Characteristics Param. No. Sym Characteristic Industrial (I): TAMB = -40°C to +85°C Extended (E): TAMB = -40°C to +125°C VDD = 2.7V to 5.5V Min Max Units Conditions thCLKOUT CLKOUT Pin High Time 15 — ns TOSC = 40 ns (Note 1) tlCLKOUT CLKOUT Pin Low Time 15 — ns TOSC = 40 ns (Note 1) trCLKOUT CLKOUT Pin Rise Time — 5 ns Measured from 0.3 VDD to 0.7 VDD (Note 1) tfCLKOUT CLKOUT Pin Fall Time — 5 ns Measured from 0.
MCP2515 TABLE 13-6: SPI INTERFACE AC CHARACTERISTICS SPI Interface AC Characteristics Param. No. Sym Characteristic VDD = 2.7V to 5.
MCP2515 NOTES: DS20001801J-page 78 2003-2019 Microchip Technology Inc.
MCP2515 14.0 PACKAGING INFORMATION 14.1 Package Marking Information 18-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC (7.50 mm) 1850256 Example: MCP2515-E/ e3 SO^^ XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 1850256 20-Lead TSSOP (4.4 mm) XXXXXXXX XXXXXNNN YYWW Example: MCP2515I/ST e3 256 1850 20-Lead QFN (4x4x0.9 mm) XXXXX XXXXXX XXXXXX YWWNNN Example: MCP 2515E/ML e3 850256 Legend: XX...
MCP2515 /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c A1 b1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK (
MCP2515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2003-2019 Microchip Technology Inc.
MCP2515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001801J-page 82 2003-2019 Microchip Technology Inc.
MCP2515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2003-2019 Microchip Technology Inc.
MCP2515 DS20001801J-page 84 2003-2019 Microchip Technology Inc.
MCP2515 2003-2019 Microchip Technology Inc.
MCP2515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001801J-page 86 2003-2019 Microchip Technology Inc.
MCP2515 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7KLFNQHVV $ 2YHUDOO :LGWK ( (
MCP2515 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS20001801J-page 88 2003-2019 Microchip Technology Inc.
MCP2515 APPENDIX A: REVISION HISTORY Revision J (January 2019) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Added Exposed Thermal Pad description to Table 1-1. Updated Section 8.1 “Oscillator Start-up Timer”. Updated Register 10-1. Updated Table 11-2. Updated Table 13-1 in Section 13.0 “Electrical Characteristics”. Updated the Product Identification System section. Revision H (November 2016) The following is the list of modifications: 1. 2.
MCP2515 NOTES: DS20001801J-page 90 2003-2019 Microchip Technology Inc.
MCP2515 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP2515 NOTES: DS20001801J-page 92 2003-2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.