Datasheet

MCP2515
DS20001801J-page 44  2003-2019 Microchip Technology Inc.
REGISTER 5-1: CNF1: CONFIGURATION REGISTER 1 (ADDRESS: 2Ah)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 SJW[1:0]: Synchronization Jump Width Length bits
11 = Length = 4 x T
Q
10 = Length = 3 x T
Q
01 = Length = 2 x T
Q
00 = Length = 1 x T
Q
bit 5-0 BRP[5:0]: Baud Rate Prescaler bits
T
Q
= 2 x (BRP[5:0] + 1)/F
OSC
.
REGISTER 5-2: CNF2: CONFIGURATION REGISTER 2 (ADDRESS: 29h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTLMODE SAM PHSEG1[2:0] PRSEG2 PRSEG1 PRSEG0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 BTLMODE: PS2 Bit Time Length bit
1 = Length of PS2 is determined by the PHSEG2[2:0] bits of CNF3
0 = Length of PS2 is the greater of PS1 and IPT (2 T
Q
s)
bit 6 SAM: Sample Point Configuration bit
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 5-3 PHSEG1[2:0]: PS1 Length bits
(PHSEG1[2:0] + 1) x T
Q
.
bit 2-0 PRSEG[2:0]: Propagation Segment Length bits
(PRSEG[2:0] + 1) x T
Q
.