Datasheet

 2003-2019 Microchip Technology Inc. DS20001801J-page 37
MCP2515
REGISTER 4-14: RXMnSIDH: MASK n STANDARD IDENTIFIER REGISTER HIGH
(ADDRESS: 20h, 24h)
(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 SID[10:3]: Standard Identifier Mask bits
These bits hold the mask bits to be applied to bits[10:3] of the Standard Identifier portion of a received
message.
Note 1: The Mask and Filter registers read all ‘0’s when in any mode except Configuration mode.
REGISTER 4-15: RXMnSIDL: MASK n STANDARD IDENTIFIER REGISTER LOW
(ADDRESS: 21h, 25h)
(1)
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
SID2 SID1 SID0
— — — EID17 EID16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 SID[2:0]: Standard Identifier Mask bits
These bits hold the mask bits to be applied to bits[2:0] of the Standard Identifier portion of a received
message.
bit 4-2 Unimplemented: Reads as ‘0’
bit 1-0 EID[17:16]: Extended Identifier Mask bits
These bits hold the mask bits to be applied to bits[17:16] of the Extended Identifier portion of a received
message.
Note 1: The Mask and Filter registers read all ‘0’s when in any mode except Configuration mode.