Datasheet
MCP2515
DS20001801J-page 34 2003-2019 Microchip Technology Inc.
4.5.3 FILHIT BITS
Filter matches on received messages can be determined
by the FILHIT bits in the associated RXBnCTRL register;
FILHIT0 (RXB0CTRL[0]) for Buffer 0 and FILHIT[2:0]
(RXB1CTRL[2:0]) for Buffer 1.
The three FILHITn bits for Receive Buffer 1 (RXB1) are
coded as follows:
• 101 = Acceptance Filter 5 (RXF5)
• 100 = Acceptance Filter 4 (RXF4)
• 011 = Acceptance Filter 3 (RXF3)
• 010 = Acceptance Filter 2 (RXF2)
• 001 = Acceptance Filter 1 (RXF1)
• 000 = Acceptance Filter 0 (RXF0)
RXB0CTRL contains two copies of the BUKT bit and a
copy of the FILHIT0 bit.
The coding of the BUKT bit enables these three bits to be
used similarly to the FILHIT[2:0] (RXB1CTRL[2:0]) bits
and to distinguish a hit on filters, RXF0 and RXF1, in
either RXB0 or after a rollover into RXB1.
• 111 = Acceptance Filter 1 (RXB1)
• 110 = Acceptance Filter 0 (RXB1)
• 001 = Acceptance Filter 1 (RXB0)
• 000 = Acceptance Filter 0 (RXB0)
If the BUKT bit is clear, there are six codes
corresponding to the six filters. If the BUKT bit is set,
there are six codes corresponding to the six filters, plus
two additional codes corresponding to the RXF0 and
RXF1 filters that roll over into RXB1.
4.5.4 MULTIPLE FILTER MATCHES
If more than one acceptance filter matches, the
FILHITn bits will encode the binary value of the lowest
numbered filter that matched. For example, if filters,
RXF2 and RXF4, match, the FILHITn bits will be loaded
with the value for RXF2. This essentially prioritizes the
acceptance filters with a lower numbered filter having
higher priority. Messages are compared to filters in
ascending order of filter number. This also ensures that
the message will only be received into one buffer. This
implies that RXB0 has a higher priority than RXB1.
4.5.5 CONFIGURING THE MASKS AND
FILTERS
The Mask and Filter registers can only be modified
when the MCP2515 is in Configuration mode (see
Section 10.0 “Modes of Operation”).
FIGURE 4-5: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION
Note: ‘000’ and ‘001’ can only occur if the BUKT
bit in RXB0CTRL is set, allowing RXB0
messages to roll over into RXB1.
Note: The Mask and Filter registers read all ‘0’s
when in any mode except Configuration
mode.
Acceptance Mask Register
RxRqst
Message Assembly Buffer
RXFn
0
RXFn
1
RXFn
n
RXMn
0
RXMn
1
RXMn
n
Identifier
Acceptance Filter Register