Datasheet

 2003-2019 Microchip Technology Inc. DS20001801J-page 25

MCP2515

4.4.3 CONFIGURED AS DIGITAL OUTPUT

When used as digital outputs, the BnBFM bits

(BFPCTRL[1:0]) must be cleared and the BnBFE bits

(BFPCTRL[3:2]) must be set for the associated buffer.

In this mode, the state of the pin is controlled by the

BnBFS bits (BFPCTRL[5:4]). Writing a ‘1’ to a BnBFS

bit will cause a high level to be driven on the associated

buffer full pin, while a ‘0’ will cause the pin to drive low.

When using the pins in this mode, the state of the pin

should be modified only by using the SPI BIT MODIFY

command to prevent glitches from occurring on either

of the buffer full pins.

TABLE 4-1: CONFIGURING RXnBF PINS

FIGURE 4-2: RECEIVE BUFFER BLOCK DIAGRAM

BnBFE BnBFM BnBFS Pin Status

0XXDisabled, high-impedance

11XReceive buffer interrupt

100Digital output = 0

101Digital output = 1

Acceptance Mask

RXM1

Acceptance Filter

RXF2

Acceptance Filter

RXF3

Acceptance Filter

RXF4

Acceptance Filter

RXF5

Acceptance Mask

RXM0

Acceptance Filter

RXF0

Acceptance Filter

RXF1

Identifier

Data Field Data Field

Identifier

Note: Messages received in the MAB are initially

applied to the mask and filters of RXB0. In

addition, only one filter match occurs (e.g.,

if the message matches both RXF0 and

RXF2, the match will be for RXF0 and the

message will be moved into RXB0).