Datasheet

 2003-2019 Microchip Technology Inc. DS20001801J-page 15
MCP2515
3.0 MESSAGE TRANSMISSION
3.1 Transmit Buffers
The MCP2515 implements three transmit buffers. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into the device memory map.
The first byte, TXBnCTRL, is a control register
associated with the message buffer. The information in
this register determines the conditions under which the
message will be transmitted and indicates the status of
the message transmission (see Register 3-1).
Five bytes are used to hold the Standard and Extended
Identifiers, as well as other message arbitration infor-
mation (see Register 3-3 through Register 3-6). The
last eight bytes are for the eight possible data bytes of
the message to be transmitted (see Register 3-8).
At a minimum, the TXBnSIDH, TXBnSIDL and TXBnDLC
registers must be loaded. If data bytes are present in the
message, the TXBnDm registers must also be loaded.
If the message is to use Extended Identifiers, the
TXBnEIDm registers must also be loaded and the
EXIDE (TXBnSIDL[3]) bit set.
Prior to sending the message, the MCU must initialize
the TXnIE bit in the CANINTE register to enable or
disable the generation of an interrupt when the message
is sent.
3.2 Transmit Priority
Transmit priority is a prioritization within the MCP2515
of the pending transmittable messages. This is
independent from, and not necessarily related to, any
prioritization implicit in the message arbitration scheme
built into the CAN protocol.
Prior to sending the SOF, the priority of all buffers that
are queued for transmission is compared. The transmit
buffer with the highest priority will be sent first. For
example, if Transmit Buffer 0 has a higher priority
setting than Transmit Buffer 1, Transmit Buffer 0 will be
sent first.
If two buffers have the same priority setting, the buffer
with the highest buffer number will be sent first. For
example, if Transmit Buffer 1 has the same priority
setting as Transmit Buffer 0, Transmit Buffer 1 will be
sent first.
There are four levels of transmit priority. If the TXP[1:0]
bits (TXBnCTRL[1:0]) for a particular message buffer
are set to ‘11’, that buffer has the highest possible pri-
ority. If the TXP[1:0] bits for a particular message buffer
are ‘00’, that buffer has the lowest possible priority.
3.3 Initiating Transmission
In order to initiate message transmission, the TXREQ
bit (TXBnCTRL[3]) must be set for each buffer to be
transmitted. This can be accomplished by:
• Writing to the register via the SPI write command
• Sending the SPI RTS command
• Setting the
TXnRTS pin low for the particular
transmit buffer(s) that are to be transmitted
If transmission is initiated via the SPI interface, the
TXREQ bit can be set at the same time as the TXPx
priority bits.
When TXREQ is set, the ABTF, MLOA and TXERR bits
(TXBnCTRL[5:4]) will be cleared automatically.
Once the transmission has completed successfully, the
TXREQ bit will be cleared, the TXnIF bit (CANINTF) will
be set and an interrupt will be generated if the TXnIE bit
(CANINTE) is set.
If the message transmission fails, the TXREQ bit will
remain set. This indicates that the message is still
pending for transmission and one of the following
condition flags will be set:
• If the message started to transmit but
encountered an error condition, the TXERR
(TXBnCTRL[4]) and MERRF bits (CANINTF[7])
will be set, and an interrupt will be generated on
the
INT pin if the MERRE bit (CANINTE[7]) is set
• If the message is lost, arbitration at the
MLOA bit (TXBnCTRL[5]) will be set
3.4 One-Shot Mode
One-Shot mode ensures that a message will only
attempt to transmit one time. Normally, if a CAN
message loses arbitration, or is destroyed by an error
frame, the message is retransmitted. With One-Shot
mode enabled, a message will only attempt to transmit
one time, regardless of arbitration loss or error frame.
One-Shot mode is required to maintain time slots in
deterministic systems, such as TTCAN.
Note: The TXREQ bit (TXBnCTRL[3]) must be
clear (indicating the transmit buffer is not
pending transmission) before writing to
the transmit buffer.
Note: Setting the TXREQ bit (TXBnCTRL[3])
does not initiate a message transmission.
It merely flags a message buffer as being
ready for transmission. Transmission will
start when the device detects that the bus
is available.
Note: If One-Shot mode is enabled (OSM bit
(CANCTRL[3])), the above conditions will
still exist. However, the TXREQ bit will be
cleared and the message will not attempt
transmission a second time.