Datasheet

MCP23017/MCP23S17
DS20001952C-page 24  2005-2016 Microchip Technology Inc.
3.5.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches. A read from this register results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
3.6 Interrupt Logic
If enabled, the MCP23X17 activates the INTn interrupt
output when one of the port pins changes state or when
a pin does not match the preconfigured default. Each
pin is individually configurable as follows:
• Enable/disable interrupt via GPINTEN
• Can interrupt on either pin change or change from
default as configured in DEFVAL
Both conditions are referred to as Interrupt-on-Change
(IOC).
The interrupt control module uses the following
registers/bits:
• IOCON.MIRROR – controls if the two interrupt
pins mirror each other
• GPINTEN – Interrupt enable register
• INTCON – controls the source for the IOC
• DEFVAL – contains the register default for IOC
operation
3.6.1 INTA AND INTB
There are two interrupt pins: INTA and INTB. By
default, INTA is associated with GPAn pins (PORTA)
and INTB is associated with GPBn pins (PORTB).
Each port has an independent signal which is cleared if
its associated GPIO or INTCAP register is read.
3.6.1.1 Mirroring the INT pins
Additionally, the INTn pins can be configured to mirror
each other so that any interrupt will cause both pins to
go active. This is controlled via IOCON.MIRROR.
If IOCON.MIRROR = 0, the internal signals are routed
independently to the INTA and INTB pads.
If IOCON.MIRROR = 1, the internal signals are OR’ed
together and routed to the INTn pads. In this case, the
interrupt will only be cleared if the associated GPIO or
INTCAP is read (see Table 3-6).
3.6.2 IOC FROM PIN CHANGE
If enabled, the MCP23X17 generates an interrupt if a
mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. Refer to Registers 3-3 and 3-5.
3.6.3 IOC FROM REGISTER DEFAULT
If enabled, the MCP23X17 generates an interrupt if a
mismatch occurs between the DEFVAL register and
the port. Only IOC enabled pins are compared. Refer to
Registers 3-3, 3-4 and 3-5.
REGISTER 3-11: OLAT: OUTPUT LATCH REGISTER 0 (ADDR 0x0A)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OL<7:0>: Reflects the logic level on the output latch <7:0>
1 = Logic-high
0 = Logic-low
TABLE 3-6: INTERRUPT OPERATION
(IOCON.MIRROR = 1)
Interrupt
Condition
Read PORTn
(1)
Interrupt
Result
GPIOA
PORTA Clear
PORTB Unchanged
GPIOB
PORTA Unchanged
PORTB Clear
GPIOA and
GPIOB
PORTA Unchanged
PORTB Unchanged
Both PORTA and
PORTB
Clear
Note 1: PORTn = GPIOn or INTCAPn