Datasheet

MCP23017/MCP23S17
DS20001952C-page 22  2005-2016 Microchip Technology Inc.
3.5.7 PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU register controls the pull-up resistors for the
port pins. If a bit is set and the corresponding pin is
configured as an input, the corresponding port pin is
internally pulled up with a 100 k resistor.
3.5.8 INTERRUPT FLAG REGISTER
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the interrupt.
This register is read-only. Writes to this register will be
ignored.
REGISTER 3-7: GPPU: GPIO PULL-UP RESISTOR REGISTER (ADDR 0x06)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PU<7:0> Controls the weak pull-up resistors on each pin (when configured as an input)
1 = Pull-up enabled
0 = Pull-up disabled
REGISTER 3-8: INTF: INTERRUPT FLAG REGISTER (ADDR 0x07)
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 INT<7:0>: Reflects the interrupt condition on the port. It reflects the change only if interrupts are
enabled per GPINTEN<7:0>.
1 = Pin caused interrupt.
0 = Interrupt not pending