MCP23017/MCP23S17 16-Bit I/O Expander with Serial Interface • Configurable Interrupt Source: - Interrupt-on-change from configured register defaults or pin changes • Polarity Inversion Register to Configure the Polarity of the Input Port Data • External Reset Input • Low Standby Current: 1 µA (max.) • Operating Voltage: - 1.8V to 5.5V @ -40°C to +85°C - 2.7V to 5.5V @ -40°C to +85°C - 4.5V to 5.
MCP23017/MCP23S17 Functional Block Diagram MCP23S17 CS SCK SI SO SPI MCP23017 SCL SDA 2 I C 3 A2:A0 GPIO GPA7 GPA6 GPA5 GPA4 GPA3 GPA2 GPA1 GPA0 Decode RESET INTA INTB GPIO GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Serializer/ Deserializer Control 16 Interrupt Logic 8 Configuration/ Control Registers DS20001952C-page 2 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature ...............................................................................................................................-65°C to +150°C Voltage on VDD with respect to VSS .................................................................................
MCP23017/MCP23S17 1.1 DC Characteristics TABLE 1-1: DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C Param. No. Characteristic Sym. Min. Typ.(1) Max. Units Conditions D001 Supply Voltage VDD 1.8 — 5.5 V D002 VDD Start Voltage to ensure Power-on Reset VPOR — VSS — V D003 VDD Rise Rate to ensure Power-on Reset SVDD 0.
MCP23017/MCP23S17 1.2 AC Characteristics FIGURE 1-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS VDD Pin 1 k SCL and SDA pin MCP23017 50 pF 135 pF FIGURE 1-2: RESET AND DEVICE RESET TIMER TIMING VDD RESET 30 32 Internal RESET 34 Output pin TABLE 1-2: DEVICE RESET SPECIFICATIONS AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C Param. No. Characteristic Sym. Min. Typ. (1) Max.
MCP23017/MCP23S17 I2C BUS START/STOP BITS TIMING FIGURE 1-3: SCL 93 91 90 92 SDA Stop Condition Start Condition I2C BUS DATA TIMING FIGURE 1-4: 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out TABLE 1-3: I2C BUS DATA REQUIREMENTS I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C, RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF Param. No. 100 Characteristic Clock High Time: Sym. — µs 1.8V – 5.5V 0.6 — — µs 2.
MCP23017/MCP23S17 TABLE 1-3: I2C BUS DATA REQUIREMENTS (CONTINUED) I2C Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C, RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF Param. No. Characteristic Sym. 90 START Condition Setup Time: TSU:STA Min. Typ. 100 kHz mode 4.7 — — µs 1.8V – 5.5V 400 kHz mode 0.6 — — µs 2.7V – 5.5V 0.16 — — µs 4.5V – 5.5V 100 kHz mode 4.0 — — µs 1.8V – 5.5V 400 kHz mode 0.6 — — µs 2.7V – 5.5V 0.
MCP23017/MCP23S17 FIGURE 1-5: SPI INPUT TIMING 3 CS (1) 11 10 6 1 2 7 Mode 1,1 SCK Mode 0,0 4 5 SI MSB in LSB in High-Impedance SO Note 1: When using SPI Mode 1,1 the CS pin needs to be toggled once before the first communication after power-up. FIGURE 1-6: SPI OUTPUT TIMING CS 8 2 9 SCK Mode 1,1 Mode 0,0 12 14 13 SO MSB out LSB out Don’t Care SI TABLE 1-4: SPI INTERFACE REQUIREMENTS SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.
MCP23017/MCP23S17 TABLE 1-4: SPI INTERFACE REQUIREMENTS (CONTINUED) SPI Interface AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C Param. No. 5 Characteristic Data Hold Time Sym. Min. Typ. Max. Units Conditions THD 20 — — ns 1.8V – 5.5V 10 — — ns 2.7V – 5.5V — 2 µs Note 1 6 CLK Rise Time TR — 7 CLK Fall Time TF — — 2 µs Note 1 8 Clock High Time THI 90 — — ns 1.8V – 5.5V 45 — — ns 2.7V – 5.5V 90 — — ns 1.8V – 5.
MCP23017/MCP23S17 TABLE 1-5: GP AND INT PINS REQUIREMENTS GP and INT Pins AC Characteristics: Unless otherwise noted, 1.8V VDD 5.5V at -40C TA +125C Param. No. Characteristic Sym. Min. Typ. Max.
MCP23017/MCP23S17 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PINOUT DESCRIPTION QFN SOIC SPDIP SSOP Pin Type Function GPB0 25 1 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB1 26 2 I/O Bidirectional I/O pin. Can be enabled for interrupt-on-change and/or internal weak pull-up resistor. GPB2 27 3 I/O Bidirectional I/O pin.
MCP23017/MCP23S17 3.0 DEVICE OVERVIEW The MCP23017/MCP23S17 (MCP23X17) device family provides 16-bit, general purpose parallel I/O expansion for I2C bus or SPI applications. The two devices differ only in the serial interface: • MCP23017 – I2C interface • MCP23S17 – SPI interface The MCP23X17 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B).
MCP23017/MCP23S17 3.2.1 BYTE MODE AND SEQUENTIAL MODE These two modes are not to be confused with single writes/reads and continuous writes/reads that are serial protocol sequences. For example, the device may be configured for Byte mode and the master may perform a continuous read. In this case, the MCP23X17 would not increment the Address Pointer and would repeatedly drive data from the same location. The MCP23X17 family has the ability to operate in Byte mode or Sequential mode (IOCON.SEQOP).
MCP23017/MCP23S17 3.2.2.2 I2C Read Operation I2C Read operations include the control byte sequence, as shown in Figure 3-2. This sequence is followed by another control byte (including the Start condition and ACK) with the R/W bit set (R/W = 1). The MCP23017 then transmits the data contained in the addressed register. The sequence is ended with the master generating a Stop or Restart condition. FIGURE 3-2: 3.2.2.
MCP23017/MCP23S17 3.2.3 SPI INTERFACE 3.2.3.1 four fixed bits and three user-defined hardware address bits (pins A2, A1 and A0). Figure 3-4 shows the control byte format. SPI Write Operation The SPI write operation is started by lowering CS. The Write command (slave address with R/W bit cleared) is then clocked into the device. The opcode is followed by an address and at least one data byte. 3.2.3.2 3.3.2 ADDRESSING SPI DEVICES (MCP23S17) The MCP23S17 is a slave SPI device.
MCP23017/MCP23S17 FIGURE 3-7: SPI ADDRESSING REGISTERS CS 0 1 0 0 A2 * A1 * A0 * R/W A7 A6 A5 Device Opcode A4 A3 A2 A1 A0 Register Address * Address pins are enabled/disabled via IOCON.HAEN. 3.4 GPIO Port Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port. The GPIO module is a general purpose, 16-bit wide, bidirectional port that is functionally split into two 8-bit wide ports.
MCP23017/MCP23S17 3.5 Configuration and Control Registers associated with PORTB. One register (IOCON) is shared between the two ports. The PORTA registers are identical to the PORTB registers, therefore, they will be referred to without differentiating between the port designation (i.e., they will not have the “A” or “B” designator assigned) in the register tables. There are 21 registers associated with the MCP23X17, as shown in Tables 3-4 and3-5.
MCP23017/MCP23S17 TABLE 3-5: CONTROL REGISTER SUMMARY (IOCON.
MCP23017/MCP23S17 3.5.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls interrupt-on-change feature for each pin. the If a bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change.
MCP23017/MCP23S17 3.5.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature. If a bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register. If a bit value is clear, the corresponding I/O pin is compared against the previous value.
MCP23017/MCP23S17 The Open-Drain (ODR) control bit enables/disables the INT pin for open-drain configuration. Setting this bit overrides the INTPOL bit. REGISTER 3-6: The Interrupt Polarity (INTPOL) sets the polarity of the INT pin. This bit is functional only when the ODR bit is cleared, configuring the INT pin as active push-pull.
MCP23017/MCP23S17 3.5.7 PULL-UP RESISTOR CONFIGURATION REGISTER The GPPU register controls the pull-up resistors for the port pins. If a bit is set and the corresponding pin is configured as an input, the corresponding port pin is internally pulled up with a 100 k resistor.
MCP23017/MCP23S17 3.5.9 INTERRUPT CAPTURED REGISTER The INTCAP register captures the GPIO port value at the time the interrupt occurred. The register is read-only and is updated only when an interrupt occurs. The register remains unchanged until the interrupt is cleared via a read of INTCAP or GPIO.
MCP23017/MCP23S17 3.5.11 OUTPUT LATCH REGISTER (OLAT) The OLAT register provides access to the output latches. A read from this register results in a read of the OLAT and not the port itself. A write to this register modifies the output latches that modifies the pins configured as outputs.
MCP23017/MCP23S17 3.6.4 INTERRUPT OPERATION The INTn interrupt output can be configured as active-low, active-high or open-drain via the IOCON register. Only those pins that are configured as an input (IODIR register) with Interrupt-On-Change (IOC) enabled (IOINTEN register) can cause an interrupt. Pins defined as an output have no effect on the interrupt output pin.
MCP23017/MCP23S17 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 28-Lead QFN Example: 23017 E/ML e3 1628256 28-Lead SOIC Example: MCP23017-E/SO e3 1628256 28-Lead SPDIP Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNN 28-Lead SSOP Example: XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
MCP23017/MCP23S17 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 DS20001952C-page 28 2005-2016 Microchip Technology Inc.
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MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001952C-page 30 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001952C-page 32 2005-2016 Microchip Technology Inc.
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MCP23017/MCP23S17 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 NOTES: DS20001952C-page 36 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 APPENDIX A: REVISION HISTORY Revision C (July 2016) The following is the list of modifications: 1. 2. 3. 4. Added ESD data to Section 1.0, Electrical Characteristics. Updated Table 2-1. Updated package outline drawings. Minor typographical errors Revision B (February 2007) 1. 2. 3. 4. Changed Byte and Sequential Read in Figure 1-1 from “R” to “W”. Table 2-4, Param No. 51 and 53: Changed from 450 to 600 and 500 to 600, respecively. Added disclaimers to package outline drawings.
MCP23017/MCP23S17 NOTES: DS20001952C-page 38 2005-2016 Microchip Technology Inc.
MCP23017/MCP23S17 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP23017/MCP23S17 NOTES: DS20001952C-page 40 2005-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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