Datasheet

2007 Microchip Technology Inc. DS22070A-page 17
MCP1824/MCP1824S
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Shutdown Control Input (SHDN)
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN
input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN
input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN
input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.2 Input Voltage Supply (V
IN
)
Connect the unregulated or regulated input voltage
source to V
IN
. If the input voltage source is located
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications. The
type of capacitor used can be ceramic, tantalum, or
aluminum electrolytic. The low ESR characteristics of
the ceramic capacitor will yield better noise and PSRR
performance at high frequency.
3.3 Ground (GND)
For the optimal Noise and Power Supply Rejection
Ratio (PSRR) performance, the GND pin of the LDO
should be tied to an electrically quiet circuit ground.
This will help the LDO power supply rejection ratio and
noise performance. The ground pin of the LDO only
conducts the ground current of the LDO, so a heavy
trace is not required. For applications that have
switching or noisy inputs, tie the GND pin to the return
of the output capacitor. Ground planes help lower
inductance and voltage spikes caused by fast transient
load currents and are recommended for applications
that are subjected to fast load transients.
3.4 Regulated Output Voltage (V
OUT
)
The V
OUT
pin is the regulated output voltage of the
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1824/MCP1824S is
stable with ceramic, tantalum, and aluminum-
electrolytic capacitors. See Section 4.3 “Output
Capacitor” for output capacitor selection guidance.
3.5 Power Good Output (PWRGD)
For fixed applications, the PWRGD output is an open-
drain output used to indicate when the LDO output
voltage is within 92% (typically) of its nominal
regulation value. The PWRGD threshold has a typical
hysteresis value of 2%. The PWRGD output is delayed
by 110 µs (typical) from the time the LDO output is
within 92% + 3% (maximum hysteresis) of the
regulated output value on power-up. This delay time is
internally fixed.
3.6 Output Voltage Adjust Input (ADJ)
For adjustable applications, the output voltage is
connected to the ADJ input through a resistor divider
that sets the output voltage regulation value. This
provides the users the capability to set the output
voltage to any value they desire within the 0.8V to 5.0V
range of the device.
3.7 Exposed Pad (EP)
The SOT-223 package has an exposed metal pad on
the bottom of the package. The exposed metal pad
gives the device better thermal characteristics by
providing a good thermal path to either the PCB or
heatsink to remove heat from the device. The exposed
pad of the package is at ground potential.
SOT-223 SOT-23
Name Description
3-Pin
Fixed
5-Pin
Fixed
5-Pin
Adj
5-Pin
Fixed
5-Pin
Adj
—
1 1 3 3 SHDN Shutdown Control Input (active-low)
12211V
IN
Input Voltage Supply
23322GNDGround
34455V
OUT
Regulated Output Voltage
—
5
—
4
—
PWRGD Power Good Output
——
5
—
4 ADJ Output Voltage Adjust/Sense Input
Exposed
Pad
Exposed
Pad
Exposed
Pad
——
EP Exposed Pad of the Package (ground potential)