Datasheet

MCP1755/1755S
DS25160A-page 18  2012 Microchip Technology Inc.
4.5 Power Good Output (PWRGD)
The open drain PWRGD output is used to indicate
when the output voltage of the LDO is within 92%
(typical value, see Section 1.0 “Electrical
Characteristics” for Minimum and Maximum
specifications) of its nominal regulation value.
As the output voltage of the LDO rises, the open-drain
PWRGD output will actively be held low until the output
voltage has exceeded the power good threshold plus
the hysteresis value. Once this threshold has been
exceeded, the power good time delay is started (shown
as T
PG
in the AC/DC Characteristics table). The
power good time delay is fixed at 100 µs (typical). After
the time delay period, the PWRGD open-drain output
becomes inactive and may be pulled high by an
external pullup resistor, indicating that the output
voltage is stable and within regulation limits. The power
good output is typically pulled up to V
IN
or V
OUT
. Pulling
the signal up to V
OUT
conserves power during
Shutdown mode.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 200 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN
input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
a minimum of 5 mA (V
PWRGD
<0.45V).
FIGURE 4-2: Power Good Timing.
FIGURE 4-3: Power Good Timing from
Shutdown.
4.6 Shutdown Input (SHDN)
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN
threshold is a fixed
voltage level. The minimum value of this shutdown
threshold required to turn the output ON is 2.4V. The
maximum value required to turn the output OFF is 0.8V.
The SHDN
input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN
input, the shutdown
circuitry has a 135 µs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN
input signal. After
the 135 µs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN
input signal is pulled low during the 135 µs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN
input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
typically 235 µs. See Figure 4-4 for a timing diagram of
the SHDN
input.
T
PG
TV
DET_PWRGD
V
PWRGD_TH
V
OUT
PWRGD
V
OL
V
OH
V
IN
SHDN
V
OUT
T
DELAY_SHDN
PWRGD
T
PG
C
LOAD
=1.0µF