Datasheet

LAN9514/LAN9514I
DS00002306A-page 44 2009-2016 Microchip Technology Inc.
4.5.4 JTAG TIMING
This section specifies the JTAG timing of the device.
TABLE 4-8: EEPROM TIMING VALUES
Symbol Description Min TYP Max Units
t
ckcyc
EECLK Cycle time 1110 1130 ns
t
ckh
EECLK High time 550 570 ns
t
ckl
EECLK Low time 550 570 ns
t
cshckh
EECS high before rising edge of EECLK 1070 ns
t
cklcsl
EECLK falling edge to EECS low 30 ns
t
dvckh
EEDO valid before rising edge of EECLK 550 ns
t
ckhdis
EEDO disable after rising edge EECLK 550 ns
t
dsckh
EEDI setup to rising edge of EECLK 90 ns
t
dhckh
EEDI hold after rising edge of EECLK 0 ns
t
ckldis
EECLK low to data disable (OUTPUT) 580 ns
t
cshdv
EEDIO valid after EECS high (VERIFY) 600 ns
t
dhcsl
EEDIO hold after EECS low (VERIFY) 0 ns
t
csl
EECS low 1070 ns
FIGURE 4-3: JTAG TIMING
TCK (Input)
TDI, TMS (Inputs)
t
tckhl
t
tckp
t
tckhl
t
su
t
h
t
dov
TDO (Output)
t
doh