Datasheet

LAN9514/LAN9514I
DS00002306A-page 4  2009-2016 Microchip Technology Inc.
1.0 INTRODUCTION
1.1 Block Diagram
1.1.1 OVERVIEW
The LAN9514/LAN9514i is a high performance Hi-Speed USB 2.0 hub with a 10/100 Ethernet controller. With applica-
tions ranging from embedded systems, desktop PCs, notebook PCs, printers, game consoles, and docking stations, the
LAN9514/LAN9514i is targeted as a high performance, low cost USB/Ethernet and USB/USB connectivity solution.
The LAN9514/LAN9514i contains an integrated USB 2.0 hub, four integrated downstream USB 2.0 PHYs, an integrated
upstream USB 2.0 PHY, a 10/100 Ethernet PHY, a 10/100 Ethernet Controller, a TAP controller, and a EEPROM con-
troller. A block diagram of the LAN9514/LAN9514i is provided in Figure 1-1.
The LAN9514/LAN9514i hub provides over 30 programmable features, including:
• PortMap (also referred to as port remap) which provides flexible port mapping and disabling sequences. The
downstream ports of the LAN9514/LAN9514i hub can be reordered or disabled in any sequence to support multi-
ple platform designs’ with minimum effort. For any port that is disabled, the LAN9514/LAN9514i automatically
reorders the remaining ports to match the USB host controller’s port numbering scheme.
• PortSwap which adds per-port programmability to USB differential pair pin locations. PortSwap allows direct
alignment of USB signals (D+/D-) to connectors avoiding uneven trace length or crossing of the USB differential
signals on the PCB.
• PHYBoost which enables four programmable levels of USB signal drive strength in USB port transceivers. PHY-
Boost attempts to restore USB signal integrity that has been compromised by system level variables such as poor
PCB layout, long cables, etc.
1.1.2 USB HUB
The integrated USB hub is fully compliant with the USB 2.0 Specification and will attach to a USB host as a Full-Speed
Hub or as a Full-/High-Speed Hub. The hub supports Low-Speed, Full-Speed, and High-Speed (if operating as a High-
Speed hub) downstream devices on all of the enabled downstream ports.
A dedicated Transaction Translator (TT) is available for each downstream facing port. This architecture ensures maxi-
mum USB throughput for each connected device when operating with mixed-speed peripherals.
The hub works with an external USB power distributed switch device to control V
BUS
switching to downstream ports,
and to limit current and sense over-current conditions.
FIGURE 1-1: INTERNAL BLOCK DIAGRAM
TAP
Controller
EEPROM
Controller
10/100
Ethernet
Controller
USB 2.0
Hub
LAN9514/LAN9514i
Ethernet
EEPROM
JTAG
USB
DP/DM
Downstream
USB PHY
Ethernet
PHY
Upstream
USB PHY
Downstream
USB PHY
Downstream
USB PHY
Downstream
USB PHY
USB
DP/DM
USB
DP/DM
USB
DP/DM
USB
DP/DM