Datasheet
2013-2015 Microchip Technology Inc. DS00001987A-page 9
LAN8740A/LAN8740Ai
1 Receive
Data 3
(MII Mode)
RXD3 VO8 Bit 3 of the 4 (in MII mode) data bits that are sent by
the transceiver on the receive path.
Note: This signal is not used in RMII mode.
PHY Address 2
Configuration
Strap
PHYAD2
VIS
(PD)
Combined with PHYAD0 and PHYAD1, this config-
uration strap sets the transceiver’s SMI address.
See Note 1 for more information on configuration
straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration" for addi-
tional information.
1 Receive Error RXER VO8 This signal is asserted to indicate that an error was
detected somewhere in the frame presently being
transferred from the transceiver. This signal is also
used in EEE mode as RXER when RXDV = 1, and
as LPI when RXDV = 0.
Note: This signal is optional in RMII mode.
Receive
Data 4
(MII Mode)
RXD4 VO8 In Symbol Interface (5B decoding) mode, this sig-
nal is the MII Receive Data 4 signal, the MSB of the
received 5-bit symbol code-group.
Note: Unless configured to the Symbol Inter-
face mode, this pin functions as RXER.
PHY Address 0
Configuration
Strap
PHYAD0
VIS
(PD)
Combined with PHYAD1 and PHYAD2, this config-
uration strap sets the transceiver’s SMI address.
See Note 1 for more information on configuration
straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration" for addi-
tional information.
1 Receive Clock
(MII Mode)
RXCLK VO8 In MII mode, this pin is the receive clock output.
• MII (100BASE-TX): 25 MHz
• MII (10BASE-T): 2.5 MHz
PHY Address 1
Configuration
Strap
PHYAD1
VIS
(PD)
Combined with PHYAD0 and PHYAD2, this config-
uration strap sets the transceiver’s SMI address.
See Note 1 for more information on configuration
straps.
Note: Refer to Section 3.7.1, "PHYAD[2:0]:
PHY Address Configuration" for addi-
tional information.
1 Receive Data
Valid
RXDV VO8 Indicates that recovered and decoded data is avail-
able on the RXD pins.
TABLE 2-1: MII/RMII SIGNALS (CONTINUED)
Num Pins Name Symbol Buffer Type Description