Datasheet

LAN8740A/LAN8740Ai
DS00001987A-page 8  2013-2015 Microchip Technology Inc.
1 Receive
Data 0
RXD0 VO8 Bit 0 of the 4 (2 in RMII mode) data bits that are
sent by the transceiver on the receive path.
PHY Operat-
ing Mode 0
Configuration
Strap
MODE0
VIS
(PU)
Combined with MODE1 and MODE2, this configu-
ration strap sets the default PHY mode.
See Note 1 for more information on configuration
straps.
Note: Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration" for additional
details.
1 Receive
Data 1
RXD1 VO8 Bit 1 of the 4 (2 in RMII mode) data bits that are
sent by the transceiver on the receive path.
PHY Operat-
ing Mode 1
Configuration
Strap
MODE1
VIS
(PU)
Combined with MODE0 and MODE2, this configu-
ration strap sets the default PHY mode.
See Note 1 for more information on configuration
straps.
Note: Refer to Section 3.7.2, "MODE[2:0]:
Mode Configuration" for additional
details.
1 Receive
Data 2
(MII Mode)
RXD2 VO8 Bit 2 of the 4 (in MII mode) data bits that are sent by
the transceiver on the receive path.
Note: This signal is not used in RMII mode.
Power Man-
agement Event
Output
nPME VO8 When in RMII mode, this pin may be used alterna-
tively as an active low Power Management Event
(PME) output.
Note: The nPME signal can be optionally con-
figured to output on the LED1, LED2, or
RXD2/nPME/nINTSEL
pins. Refer to
Section 3.8.4, "Wake on LAN (WoL)" for
additional nPME and WoL information.
MII/RMII Mode
Select Configu-
ration Strap
RMIISEL VIS
(PD)
This configuration strap selects the MII or RMII
mode of operation. When strapped low to VSS, MII
mode is selected. When strapped high to VDDIO
RMII mode is selected.
See Note 1 for more information on configuration
straps.
Note: Refer to Section 3.7.3, "RMIISEL:
MII/RMII Mode Configuration" for addi-
tional details.
TABLE 2-1: MII/RMII SIGNALS (CONTINUED)
Num Pins Name Symbol Buffer Type Description