Datasheet

 2013-2015 Microchip Technology Inc. DS00001987A-page 47
LAN8740A/LAN8740Ai
FIGURE 3-13: TDR USAGE FLOW DIAGRAM
Disable AMDIX and Force MDI (or MDIX)
Write PHY Reg 27: 0x8000 (MDI)
- OR -
Write PHY Reg 27: 0xA000 (MDIX)
TDR Channel Status Complete?
Disable ANEG and Force 100Mb Full-
Duplex
Write PHY Reg 0: 0x2100
Enable TDR
Write PHY Reg 25: 0x8000
NO
Reg 25.8 == 0
YES
Reg 25.8 == 1
Check TDR Control/Status Register
Read PHY Reg 25: 0x8000
Save:
TDR Channel Type (Reg 25.10:9)
TDR Channel Length (Reg 25.7:0)
MDIX Case Tested?
YES
Repeat Testing
in MDIX Mode
Done
Start