Datasheet

 2013-2015 Microchip Technology Inc. DS00001987A-page 123
LAN8740A/LAN8740Ai
5.6.4.1 RMII CLKIN Requirements
5.6.5 SMI TIMING
This section specifies the SMI timing of the device. Please refer to Section 3.5, "Serial Management Interface (SMI)" for
additional details.
TABLE 5-13: RMII CLKIN (REF_CLK) TIMING VALUES
Parameter Min. Typ. Max. Unit Note
CLKIN frequency 50 MHz
CLKIN Frequency Drift ±50 ppm
CLKIN Duty Cycle 40 60 %
CLKIN Jitter 150 ps p-p – not RMS
FIGURE 5-7: SMI TIMING
TABLE 5-14: SMI TIMING VALUES
Symbol Description Min. Max. Unit
t
clkp
MDC period 400 ns
t
clkh
MDC high time 160 (80%) ns
t
clkl
MDC low time 160 (80%) ns
t
val
MDIO (read from PHY) output valid from rising edge of MDC 300 ns
t
oinvld
MDIO (read from PHY) output invalid from rising edge of MDC 0 ns
t
su
MDIO (write to PHY) setup time to rising edge of MDC 10 ns
t
ihold
MDIO (write to PHY) input hold time after rising edge of MDC 10 ns
MDC
MDIO
t
clkh
t
clkl
t
clkp
t
oinvld
MDIO
t
su
t
ihold
(Data-Out)
(Data-In)
t
oinvld
t
val
(INPUT)