Datasheet

 2013-2015 Microchip Technology Inc. DS00001987A-page 121
LAN8740A/LAN8740Ai
5.6.3.1 100 Mbps Internal Loopback MII Timing
FIGURE 5-5: 100 MBPS INTERNAL LOOPBACK MII TIMING
TABLE 5-11: 100 MBPS INTERNAL LOOPBACK MII TIMING VALUES
Symbol Description Min. Typ. Max. Unit
t
1
TXCLK rising edge after TXEN assertion to
RXDV assertion
(100 Mbps internal loopback MII mode)
160 161 162 ns
Note: The t
1
measurement applies in MII mode when the Loopback bit of the Basic Control Register is set to “1”
and a link has been established in 100 Mb full-duplex mode. The t
1
measurement is taken from the first
rising edge of TXCLK following assertion of TXEN to the rising edge of RXDV.
TXCLK
(OUTPUT)
RXD[3:0]
(OUTPUTS)
TXEN
(INPUT)
t
1
RXDV
(OUTPUT)