Datasheet

LAN8740A/LAN8740Ai
DS00001987A-page 120  2013-2015 Microchip Technology Inc.
Note 1: 40 ns for 100BASE-TX operation, 400 ns for 10BASE-T operation.
2: Timing was designed for system load between 10 pF and 25 pF.
FIGURE 5-4: MII TRANSMIT TIMING
TABLE 5-10: MII TRANSMIT TIMING VALUES
Symbol Description Min. Typ. Max. Unit Note
t
clkp
TXCLK period (see Note 1)ns
t
clkh
TXCLK high time t
clkp
* 0.4 t
clkp
* 0.6 ns
t
clkl
TXCLK low time t
clkp
* 0.4 t
clkp
* 0.6 ns
t
su
TXD[3:0], TXEN, TXER setup time
to rising edge of TXCLK
12.0 ns (see Note 2)
t
hold
TXD[3:0], TXEN, TXER hold time
after rising edge of TXCLK
0ns(see Note 2)
t
1
TXCLK rising edge after TXEN
assertion to RXDV assertion
(100 Mbps internal loopback
mode)
160 162 ns (see Note 2)
t
su
t
clkh
t
clkl
t
clkp
t
hold
t
su
t
hold
t
hold
t
su
t
hold
TXCLK
(OUTPUT)
TXD[3:0]
(INPUTS)
TXEN, TXER
(INPUTS)