Datasheet

 2013-2015 Microchip Technology Inc. DS00001987A-page 119
LAN8740A/LAN8740Ai
5.6.3 MII INTERFACE TIMING
This section specifies the MII interface transmit and receive timing. Please refer to Section 3.4.1, "MII" for additional
details.
Note 1: 40 ns for 100BASE-TX operation, 400 ns for 10BASE-T operation.
2: Timing was designed for system load between 10 pF and 25 pF.
FIGURE 5-3: MII RECEIVE TIMING
TABLE 5-9: MII RECEIVE TIMING VALUES
Symbol Description Min. Typ. Max. Unit Note
t
clkp
RXCLK period (see Note 1)ns
t
clkh
RXCLK high time t
clkp
* 0.4 t
clkp
* 0.6 ns
t
clkl
RXCLK low time t
clkp
* 0.4 t
clkp
* 0.6 ns
t
val
RXD[3:0], RXDV, RXER output
valid from rising edge of RXCLK
28.0 ns (see Note 2)
t
invld
RXD[3:0], RXDV, RXER output
invalid from rising edge of RXCLK
10.0 ns (see Note 2)
RXCLK
(OUTPUT)
t
clkh
t
clkl
t
clkp
t
val
t
invld
t
val
t
val
t
invld
RXDV, RXER
(OUTPUTS)
RXD[3:0]
(OUTPUTS)