Datasheet

LAN8740A/LAN8740Ai
DS00001987A-page 118  2013-2015 Microchip Technology Inc.
5.6.2 POWER-ON nRST & CONFIGURATION STRAP TIMING
This diagram illustrates the nRST reset and configuration strap timing requirements in relation to power-on. A hardware
reset (nRST assertion) is required following power-up. For proper operation, nRST must be asserted for no less than
t
rstia.
The nRST pin can be asserted at any time, but must not be deasserted before t
purstd
after all external power sup-
plies have reached operational levels. In order for valid configuration strap values to be read at power-up, the t
css
and
t
csh
timing constraints must be followed. Refer to Section 3.8.7, "Resets" for additional information.
Note 1: 20 clock cycles for 25 MHz, or 40 clock cycles for 50 MHz
FIGURE 5-2: POWER-ON nRST & CONFIGURATION STRAP TIMING
TABLE 5-8: POWER-ON nRST & CONFIGURATION STRAP TIMING VALUES
Symbol Description Min. Typ. Max. Unit
t
purstd
External power supplies at operational level to nRST
deassertion
25 ms
t
purstv
External power supplies at operational level to nRST
valid
0ns
t
rstia
nRST input assertion time 100 µs
t
css
Configuration strap pins setup to nRST deassertion 200 ns
t
csh
Configuration strap pins hold after nRST deassertion 1 ns
t
otaa
Output tri-state after nRST assertion 50 ns
t
odad
Output drive after nRST deassertion 2 800
(see Note 1)
ns
Note: nRST deassertion must be monotonic.
Note: Device configuration straps are latched as a result of nRST assertion. Refer to Section 3.7, "Configuration
Straps" for details. Configuration straps must only be pulled high or low and must not be driven as inputs.
t
css
nRST
Configuration Strap
Pins Input
t
rstia
t
csh
Configuration Strap
Pins Output Drive
t
odad
All External
Power Supplies
t
purstd
V
opp
t
purstv
t
otaa