LAN8740A/LAN8740Ai Small Footprint MII/RMII 10/100 Energy Efficient Ethernet Transceiver with HP Auto-MDIX and flexPWR® Technology Highlights Key Benefits • Single-Chip Ethernet Physical Layer Transceiver (PHY) • Compliant with Energy Efficient Ethernet 802.3az • Cable diagnostic support • Wake on LAN (WoL) support • Comprehensive flexPWR technology - Flexible power management architecture - LVCMOS Variable I/O voltage range: +1.8 V to +3.3 V - Integrated 1.
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LAN8740A/LAN8740Ai Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 6 3.0 Functional Description ............................................................
LAN8740A/LAN8740Ai 1.0 INTRODUCTION 1.1 General Terms and Conventions The following is a list of the general terms used throughout this document: BYTE 8 bits FIFO First In First Out buffer; often used for elasticity buffer MAC Media Access Controller MII Media Independent Interface RMII™ Reduced Media Independent Interface N/A Not Applicable X Indicates that a logic state is “don’t care” or undefined. RESERVED Refers to a reserved bit field or address.
LAN8740A/LAN8740Ai The LAN8740A/LAN8740Ai is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature range versions. A typical system application is shown in Figure 1-1. Figure 1-2 provides an internal block diagram of the device.
LAN8740A/LAN8740Ai PIN DESCRIPTION AND CONFIGURATION RXP RXN TXP TXN VDD1A RXDV TXD3 31 30 29 28 27 26 25 32-VQFN PIN ASSIGNMENTS (TOP VIEW) RBIAS FIGURE 2-1: 32 2.
LAN8740A/LAN8740Ai TABLE 2-1: MII/RMII SIGNALS Num Pins Name Symbol Buffer Type 1 Transmit Data 0 TXD0 VIS The MAC transmits data to the transceiver using this signal in all modes. 1 Transmit Data 1 TXD1 VIS The MAC transmits data to the transceiver using this signal in all modes. 1 Transmit Data 2 (MII Mode) TXD2 VIS The MAC transmits data to the transceiver using this signal in MII mode.
LAN8740A/LAN8740Ai TABLE 2-1: MII/RMII SIGNALS (CONTINUED) Num Pins Name Symbol Buffer Type Description 1 Receive Data 0 RXD0 VO8 Bit 0 of the 4 (2 in RMII mode) data bits that are sent by the transceiver on the receive path. PHY Operating Mode 0 Configuration Strap MODE0 VIS (PU) Combined with MODE1 and MODE2, this configuration strap sets the default PHY mode. See Note 1 for more information on configuration straps.
LAN8740A/LAN8740Ai TABLE 2-1: MII/RMII SIGNALS (CONTINUED) Num Pins Name Symbol Buffer Type Description 1 Receive Data 3 (MII Mode) RXD3 VO8 Bit 3 of the 4 (in MII mode) data bits that are sent by the transceiver on the receive path. PHY Address 2 Configuration Strap PHYAD2 Note: VIS (PD) This signal is not used in RMII mode. Combined with PHYAD0 and PHYAD1, this configuration strap sets the transceiver’s SMI address. See Note 1 for more information on configuration straps.
LAN8740A/LAN8740Ai TABLE 2-1: MII/RMII SIGNALS (CONTINUED) Num Pins Name Symbol Buffer Type Description 1 Collision Detect (MII Mode) COL VO8 This signal is asserted to indicate detection of a collision condition in MII mode. Carrier Sense / Receive Data Valid (RMII Mode) CRS_DV VO8 This signal is asserted to indicate the receive medium is non-idle in RMII mode. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] is held low until the SFD byte (10101011) is received.
LAN8740A/LAN8740Ai TABLE 2-2: LED PINS Num Pins Name Symbol Buffer Type Description 1 LED 1 LED1 O12 This pin can be used to indicate link activity, link speed, nINT, or nPME as configured via the LED1 Function Select field of the Wakeup Control and Status Register (WUCSR). Note: Interrupt Output nINT Power Management Event Output nPME Regulator Off Configuration Strap REGOFF O12 Active low interrupt output. Note: O12 By default, the nINT signal is output on the nINT/TXER/TXD4 pin.
LAN8740A/LAN8740Ai TABLE 2-2: LED PINS (CONTINUED) Num Pins Name Symbol Buffer Type Description 1 LED 2 LED2 O12 This pin can be used to indicate link activity, link speed, nINT, or nPME as configured via the LED2 Function Select field of the Wakeup Control and Status Register (WUCSR). Note: Interrupt Output nINT Power Management Event Output nPME nINT/TXER/ TXD4 Function Select Configuration Strap nINTSEL O12 Active low interrupt output.
LAN8740A/LAN8740Ai TABLE 2-3: SERIAL MANAGEMENT INTERFACE (SMI) PINS Num Pins Name Symbol Buffer Type 1 SMI Data Input/Output MDIO VIS/ VO8 (PU) Serial Management Interface data input/output 1 SMI Clock MDC VIS Serial Management Interface clock TABLE 2-4: Description ETHERNET PINS Num Pins Name Symbol Buffer Type 1 Ethernet TX/RX Positive Channel 1 TXP AIO Transmit/Receive Positive Channel 1 1 Ethernet TX/RX Negative Channel 1 TXN AIO Transmit/Receive Negative Channel 1 1 E
LAN8740A/LAN8740Ai TABLE 2-6: ANALOG REFERENCE PINS Num Pins Name Symbol Buffer Type 1 External 1% Bias Resistor Input RBIAS AI Description This pin requires connection of a 12.1 kΩ (1%) resistor to ground. Refer to the LAN8740A/LAN8740Ai reference schematic for connection information. Note: TABLE 2-7: POWER PINS Num Pins Name Symbol Buffer Type 1 +1.8 V to +3.3 V Variable I/O Power VDDIO P +1.2 V Digital Core Power Supply VDDCR 1 The nominal voltage is 1.
LAN8740A/LAN8740Ai 2.
LAN8740A/LAN8740Ai 2.2 Buffer Types TABLE 2-9: BUFFER TYPES Buffer Type IS Description Schmitt-triggered input O12 Output with 12 mA sink and 12 mA source VIS Variable voltage Schmitt-triggered input VO8 Variable voltage output with 8 mA sink and 8 mA source VOD8 PU Variable voltage open-drain output with 8 mA sink 50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled. Note: PD 50 µA (typical) internal pull-down.
LAN8740A/LAN8740Ai 3.0 FUNCTIONAL DESCRIPTION This chapter provides functional descriptions of the various device features. These features have been categorized into the following sections: • • • • • • • • • Transceiver Auto-Negotiation HP Auto-MDIX Support MAC Interface Serial Management Interface (SMI) Interrupt Management Configuration Straps Miscellaneous Functions Application Diagrams 3.1 3.1.1 Transceiver 100BASE-TX TRANSMIT The 100BASE-TX transmit data path is shown in Figure 3-1.
LAN8740A/LAN8740Ai TABLE 3-1: 4B/5B CODE TABLE Code Group Sym Receiver Interpretation DATA Transmitter Interpretation 11110 0 0 0000 0 0000 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 A A 1010 A 1010 10111 B B 1011 B 1011 DATA 11010 C C 1100 C 1100 11011 D D 1101
LAN8740A/LAN8740Ai 3.1.1.3 Scrambling Repeated data patterns (especially the IDLE code-group) can have power spectral densities with large narrow-band peaks. Scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. This uniform spectral density is required by FCC regulations to prevent excessive EMI from being radiated by the physical wiring.
LAN8740A/LAN8740Ai 3.1.2.1 100M Receive Input The MLT-3 from the cable is fed into the transceiver (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC samples the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer, it generates 6 digital bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that the full dynamic range of the ADC can be used. 3.1.2.
LAN8740A/LAN8740Ai 3.1.2.7 Receive Data Valid Signal The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the RXD[3:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure or SIGDET becomes false.
LAN8740A/LAN8740Ai 3.1.3.1 10M Transmit Data Across the MII/RMII Interface The MAC controller drives the transmit data onto the TXD bus. For MII, when the controller has driven TXEN high to indicate valid data, the data is latched by the MII block on the rising edge of TXCLK. The data is in the form of 4-bit wide 2.5 MHz data. For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the device.
LAN8740A/LAN8740Ai 3.1.4.3 10M Receive Data Across the MII/RMII Interface For MII, the 4-bit data nibbles are sent to the MII block. In MII mode, these data nibbles are valid on the rising edge of the 2.5 MHz RXCLK. For RMII, the 2-bit data nibbles are sent to the RMII block. In RMII mode, these data nibbles are valid on the rising edge of the RMII REF_CLK. Note: 3.1.4.4 RXDV goes high with the SFD.
LAN8740A/LAN8740Ai There are 4 possible matches of the technology abilities. In the order of priority these are: • • • • 100M Full Duplex (Highest Priority) 100M Half Duplex 10M Full Duplex 10M Half Duplex (Lowest Priority) If the full capabilities of the transceiver are advertised (100M, Full Duplex), and if the link partner is capable of 10M and 100M, then auto-negotiation selects 100M as the highest performance mode.
LAN8740A/LAN8740Ai 3.3 HP Auto-MDIX Support HP Auto-MDIX facilitates the use of CAT-3 (10BASE-T) or CAT-5 (100BASE-TX) media UTP interconnect cable without consideration of interface wiring scheme. If a user plugs in either a direct connect LAN cable, or a cross-over patch cable, as shown in Figure 3-4, the device’s Auto-MDIX transceiver is capable of configuring the TXP/TXN and RXP/RXN pins for correct transceiver operation.
LAN8740A/LAN8740Ai 3.4 MAC Interface The MII/RMII block is responsible for communication with the MAC controller. Special sets of hand-shake signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit bus. The device must be configured in MII or RMII mode. This is done by specific pin strapping configurations. Refer to Section 3.4.3, "MII vs. RMII Configuration" for information on pin strapping and how the pins are mapped differently. 3.4.
LAN8740A/LAN8740Ai 3.4.2.1 CRS_DV - Carrier Sense/Receive Data Valid The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. In 10BASE-T mode when squelch is passed, or in 100BASE-TX mode when 2 non-contiguous zeroes in 10 bits are detected, the carrier is said to be detected.
LAN8740A/LAN8740Ai 3.4.3 MII VS. RMII CONFIGURATION The device must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done via the RMIISEL configuration strap. MII or RMII mode selection is configured based on the strapping of the RMIISEL configuration strap as described in Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration".
LAN8740A/LAN8740Ai 3.5 Serial Management Interface (SMI) The Serial Management Interface is used to control the device and obtain its status. This interface supports registers 0 through 6 as required by clause 22 of the 802.3 standard, as well as “vendor-specific” registers 16 to 31 allowed by the specification. Device registers are detailed in Chapter 4, "Register Descriptions". At the system level, SMI provides 2 signals: MDIO and MDC.
LAN8740A/LAN8740Ai 3.6 Interrupt Management The device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. This interrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain events are detected as setup by the Interrupt Mask Register. The nINT signal can be selected to output on three different pins: • nINT/TXER/TXD4 (See Section 3.7.
LAN8740A/LAN8740Ai 3.6.1 PRIMARY INTERRUPT SYSTEM The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The Primary interrupt system is always selected after power-up or hard reset. In this mode, to set an interrupt, set the corresponding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT output will be asserted.
LAN8740A/LAN8740Ai 3.6.2 ALTERNATE INTERRUPT SYSTEM The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register to “1”. In this mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 3-4). To Clear an interrupt, either clear the corresponding bit in the Interrupt Mask Register to deassert the nINT output, or clear the interrupt source, and write a ‘1’ to the corresponding Interrupt Source Flag.
LAN8740A/LAN8740Ai 3.7 Configuration Straps Configuration straps allow various features of the device to be automatically configured to user defined values. Configuration straps are latched upon Power-On Reset (POR) and pin reset (nRST). Configuration straps include internal resistors in order to prevent the signal from floating when unconnected.
LAN8740A/LAN8740Ai 3.7.2 MODE[2:0]: MODE CONFIGURATION The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deasserted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is then configured by the register bit values.
LAN8740A/LAN8740Ai 3.7.4 REGOFF: INTERNAL +1.2 V REGULATOR CONFIGURATION The incorporation of flexPWR technology provides the ability to disable the internal +1.2 V regulator. When the regulator is disabled, an external +1.2 V must be supplied to the VDDCR pin. Disabling the internal +1.2 V regulator makes it possible to reduce total system power, since an external switching regulator with greater efficiency (versus the internal linear regulator) can be used to provide +1.2 V to the transceiver circuitry.
LAN8740A/LAN8740Ai 3.8 3.8.1 Miscellaneous Functions LEDS Two LED signals are provided as a convenient means to indicate the transceiver's mode of operation or be used as nINT or nPME signals. The LED1 and LED2 pin functions are configurable via the LED1 Function Select and LED2 Function Select bits of the Wakeup Control and Status Register (WUCSR), respectively. When used as an LED indicator, the LED signals are either active high or active low as described in Section 3.8.1.
LAN8740A/LAN8740Ai 3.8.1.2 LED1/nINT/nPME Usage with Internal Regulator Enabled (REGOFF Low) When the LED1/nINT/nPME/REGOFF pin is low during reset, the internal regulator is enabled. After the deassertion of reset, this pin will first function as LED1 (Link Activity). Upon configuration, it can function as nINT or nPME. Figure 38 illustrates the steps required to program the LED1 pin as nINT or nPME with the internal regulator enabled.
LAN8740A/LAN8740Ai 3.8.1.4 LED2/nINT/nPME Usage with nINTSEL Disabled When the LED2/nINT/nPME/nINTSEL pin is low during reset, the nINT/TXER/TXD4 pin is configured to function as TXER/TXD4. After the deassertion of reset, this pin will first function as LED2. Upon configuration, it can function as nINT or nPME. Figure 3-10 illustrates the steps required to program the LED2 pin as nINT or nPME with nINTSEL disabled. In this configuration, it is not recommended to connect an LED to this pin.
LAN8740A/LAN8740Ai 3.8.1.6 nINTSEL and LED2 Polarity Selection The nINTSEL configuration strap is shared with the LED2 pin. The LED2 output will automatically change polarity based on the presence of an external pull-down resistor. If the LED2 pin is pulled high to VDD2A to select a logical high for nINTSEL, then the LED2 output will be active low. If the LED2 pin is pulled low by an external pull-down resistor to select a logical low for nINTSEL, the LED2 output will then be an active high output.
LAN8740A/LAN8740Ai When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover Time/EEE Configuration Register. When enabled, the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD NLP/Crossover Time/EEE Configuration Register. When in EDPD mode, the device can also be configured to wake on the reception of one or two NLPs.
LAN8740A/LAN8740Ai 3.8.4.1 Perfect DA (Destination Address) Detection When enabled, the Perfect DA detection mode allows the triggering of the nINT or nPME pin when a frame with the destination address matching the address stored in the MAC Receive Address A Register (RX_ADDRA), MAC Receive Address B Register (RX_ADDRB), and MAC Receive Address C Register (RX_ADDRC) is received. The frame must also pass the FCS and packet length check.
LAN8740A/LAN8740Ai As an example, the Host system must perform the following steps to enable the device to assert nINT on detection of a Magic Packet WoL event: 1. 2. 3. Set the desired MAC address to cause the wake event in the MAC Receive Address A Register (RX_ADDRA), MAC Receive Address B Register (RX_ADDRB), and MAC Receive Address C Register (RX_ADDRC). Set the Magic Packet Enable (MPEN) bit of the Wakeup Control and Status Register (WUCSR) to enable Magic Packet detection.
LAN8740A/LAN8740Ai As an example, the Host system must perform the following steps to enable the device to assert nINT on detection of a Wakeup Frame WoL event: Declare Pattern: 1. 2. Update the Wakeup Filter Byte Mask Registers (WUF_MASK) to indicate the valid bytes to match. Calculate the CRC-16 value of valid bytes off-line and update the Wakeup Filter Configuration Register B (WUF_CFGB). CRC-16 is calculated as follows: At the start of a frame, CRC-16 is initialized with the value FFFFh.
LAN8740A/LAN8740Ai Enable Wakeup Frame Detection: 7. 8. Set the Wakeup Frame Enable (WUEN) bit of the Wakeup Control and Status Register (WUCSR) to enable Wakeup Frame detection. Set bit 8 (WoL event indicator) in the Interrupt Mask Register to enable WoL events to trigger assertion of the nINT interrupt pin. When a match is triggered, the nINT interrupt pin will be asserted and the Remote Wakeup Frame Received (WUFR) bit of the Wakeup Control and Status Register (WUCSR) will be set.
LAN8740A/LAN8740Ai 3.8.7.1 Hardware Reset A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum time detailed in Section 5.6.2, "Power-On nRST & Configuration Strap Timing" to ensure a proper transceiver reset. During a hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal. Note: 3.8.7.2 A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.6.
LAN8740A/LAN8740Ai 3.8.11 CABLE DIAGNOSTICS The LAN8740A/LAN8740Ai provides cable diagnostics which allow for open/short and length detection of the Ethernet cable. The cable diagnostics consist of two primary modes of operation: • Time Domain Reflectometry (TDR) Cable Diagnostics TDR cable diagnostics enable the detection of open or shorted cabling on the TX or RX pair, as well as cable length estimation to the open/short fault.
LAN8740A/LAN8740Ai FIGURE 3-13: TDR USAGE FLOW DIAGRAM Start Disable ANEG and Force 100Mb FullDuplex Write PHY Reg 0: 0x2100 Disable AMDIX and Force MDI (or MDIX) Write PHY Reg 27: 0x8000 (MDI) - OR Write PHY Reg 27: 0xA000 (MDIX) Enable TDR Write PHY Reg 25: 0x8000 Check TDR Control/Status Register Read PHY Reg 25: 0x8000 NO Reg 25.8 == 0 TDR Channel Status Complete? YES Reg 25.8 == 1 Save: TDR Channel Type (Reg 25.10:9) TDR Channel Length (Reg 25.
LAN8740A/LAN8740Ai The TDR operates by transmitting pulses on the selected twisted pair within the Ethernet cable (TX in MDI mode, RX in MDIX mode). If the pair being tested is open or shorted, the resulting impedance discontinuity results in a reflected signal that can be detected by the LAN8740A/LAN8740Ai. The LAN8740A/LAN8740Ai measures the time between the transmitted signal and received reflection and indicates the results in the TDR Channel Length field of the TDR Control/Status Register.
LAN8740A/LAN8740Ai The typical cable length measurement margin of error for Open and Shorted cases is dependent on the selected cable type and the distance of the open/short from the device. Table 3-10 and Table 3-11 detail the typical measurement error for Open and Shorted cases, respectively.
LAN8740A/LAN8740Ai 3.8.11.2 Matched Cable Diagnostics Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables of up to 120 meters. If there is an active 100 Mb link, the approximate distance to the link partner can be estimated using the Cable Length Register. If the cable is properly terminated, but there is no active 100 Mb link (the link partner is disabled, nonfunctional, the link is at 10 Mb, etc.
LAN8740A/LAN8740Ai 3.8.12 LOOPBACK OPERATION The device may be configured for near-end loopback and far loopback. These loopback modes are detailed in the following subsections. 3.8.12.1 Near-end Loopback Near-end loopback mode sends the digital transmit data back out the receive data signals for testing purposes, as indicated by the blue arrows in Figure 3-14. The near-end loopback mode is enabled by setting the Loopback bit of the Basic Control Register to “1”.
LAN8740A/LAN8740Ai 3.8.12.3 Connector Loopback The device maintains reliable transmission over very short cables and can be tested in a connector loopback as shown in Figure 3-16. An RJ45 loopback cable can be used to route the transmit signals from the output of the transformer back to the receiver inputs. The loopback works at both 10 and 100 Mbps.
LAN8740A/LAN8740Ai 3.9 Application Diagrams This section provides typical application diagrams for the following: • • • • • Simplified System Level Application Diagram Power Supply Diagram (1.2 V Supplied by Internal Regulator) Power Supply Diagram (1.2 V Supplied by External Source) Twisted-Pair Interface Diagram (Single Power Supply) Twisted-Pair Interface Diagram (Dual Power Supplies) 3.9.
LAN8740A/LAN8740Ai 3.9.2 POWER SUPPLY DIAGRAM (1.2 V SUPPLIED BY INTERNAL REGULATOR) FIGURE 3-18: POWER SUPPLY DIAGRAM (1.2 V SUPPLIED BY INTERNAL REGULATOR) LAN8740A/LAN8740Ai 32-VQFN Ch.2: 3.3 V Circuitry Core Logic VDDCR 470 pF 1 uF VDDDIO Supply 1.8 - 3.3 V OUT Internal Regulator VDD2A IN CBYPASS Ch.1: 3.3 V Circuitry VDDIO CF Power Supply 3.3 V VDD1A CBYPASS CBYPASS RBIAS LED1/ REGOFF VSS 12.1k ~270 Ohm DS00001987A-page 54 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 3.9.3 POWER SUPPLY DIAGRAM (1.2 V SUPPLIED BY EXTERNAL SOURCE) FIGURE 3-19: POWER SUPPLY DIAGRAM (1.2 V SUPPLIED BY EXTERNAL SOURCE) LAN8740A/LAN8740Ai 32-VQFN Ch.2: 3.3 V Circuitry Core Logic VDDCR Supply 1.2 V VDDCR 470 pF 1 uF VDDDIO Supply 1.8 - 3.3 V OUT Internal Regulator VDD2A IN (Disabled) CBYPASS VDD1A Ch.1: 3.3 V Circuitry VDDIO CF Power Supply 3.3 V CBYPASS CBYPASS RBIAS LED1/ REGOFF VSS 12.1k ~270 Ohm 10k 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 3.9.4 TWISTED-PAIR INTERFACE DIAGRAM (SINGLE POWER SUPPLY) FIGURE 3-20: TWISTED-PAIR INTERFACE DIAGRAM (SINGLE POWER SUPPLY) LAN8740A/LAN8740Ai 32-VQFN Power Supply 3.3 V Ferrite Bead 49.9 Ohm Resistors VDD2A CBYPASS VDD1A CBYPASS Magnetics RJ45 TXP 1 2 3 4 5 6 7 8 75 Ohm TXN RXP 75 Ohm RXN 1000 pF 3 kV CBYPASS DS00001987A-page 56 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 3.9.5 TWISTED-PAIR INTERFACE DIAGRAM (DUAL POWER SUPPLIES) FIGURE 3-21: TWISTED-PAIR INTERFACE DIAGRAM (DUAL POWER SUPPLIES) LAN8740A/LAN8740Ai 32-VQFN Power Supply 3.3 V Power Supply 2.5 V - 3.3 V 49.9 Ohm Resistors VDD2A CBYPASS VDD1A CBYPASS Magnetics RJ45 TXP 1 2 3 4 5 6 7 8 75 Ohm TXN RXP 75 Ohm RXN 1000 pF 3 kV CBYPASS 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.0 REGISTER DESCRIPTIONS This chapter describes the various Control and Status Registers (CSRs) and MDIO Manageable Device (MMD) Registers. The CSRs follow the IEEE 802.3 (clause 22.2.4) management register set. The MMD registers adhere to the IEEE 802.3-2008 45.2 MDIO Interface Registers specification. All functionality and bit definitions comply with these standards. The IEEE 802.
LAN8740A/LAN8740Ai 4.2 Control and Status Registers Table 4-2 provides a list of supported registers. Register details, including bit definitions, are provided in the proceeding subsections.
LAN8740A/LAN8740Ai 4.2.1 BASIC CONTROL REGISTER Index (In Decimal): Bits 15 0 Size: 16 bits Description Soft Reset 1 = Software reset. Bit is self-clearing. When setting this bit do not set other bits in this register. Note: Type Default R/W SC 0b The configuration (as described in Section 3.7.2, "MODE[2:0]: Mode Configuration") is set from the register bit values, and not from the mode pins.
LAN8740A/LAN8740Ai 4.2.
LAN8740A/LAN8740Ai 4.2.3 PHY IDENTIFIER 1 REGISTER Index (In Decimal): 2 Size: 16 bits Bits Description Type Default 15:0 PHY ID Number Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. R/W 0007h DS00001987A-page 62 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.2.4 PHY IDENTIFIER 2 REGISTER Index (In Decimal): Bits 3 16 bits Type Default PHY ID Number Assigned to the 19th through 24th bits of the OUI. R/W C110h 9:4 Model Number Six-bit manufacturer’s model number R/W 3:0 Revision Number Four-bit manufacturer’s revision number R/W 15:10 Note: Description Size: The default value of the Revision Number field may vary dependent on the silicon revision number. 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.2.
LAN8740A/LAN8740Ai 4.2.
LAN8740A/LAN8740Ai 4.2.7 AUTO NEGOTIATION EXPANSION REGISTER Index (In Decimal): Bits 6 Size: 16 bits Type Default RESERVED RO - 6 Receive Next Page Location Able 0 = Received next page storage location is not specified by bit 6.5 1 = Received next page storage location is specified by bit 6.
LAN8740A/LAN8740Ai 4.2.8 AUTO NEGOTIATION NEXT PAGE TX REGISTER Index (In Decimal): Bits 7 Description Size: 16 bits Type Default 15 Next Page 0 = No next page ability 1 = Next page capable R/W 0b 14 RESERVED RO - 13 Message Page 0 = Unformatted page 1 = Message page R/W 1b 12 Acknowledge 2 0 = Device cannot comply with message. 1 = Device will comply with message. R/W 0b 11 Toggle 0 = Previous value was HIGH. 1 = Previous value was LOW.
LAN8740A/LAN8740Ai 4.2.9 AUTO NEGOTIATION NEXT PAGE RX REGISTER Index (In Decimal): Bits 8 Description Size: 16 bits Type Default 15 Next Page 0 = No next page ability 1 = Next page capable RO 0b 14 Acknowledge 0 = Link code word not yet received from partner 1 = Link code word received from partner RO 0b 13 Message Page 0 = Unformatted page 1 = Message page RO 0b 12 Acknowledge 2 0 = Device cannot comply with message. 1 = Device will comply with message.
LAN8740A/LAN8740Ai 4.2.10 MMD ACCESS CONTROL REGISTER Index (In Decimal): 13 Size: 16 bits This register in conjunction with the MMD Access Address/Data Register provides indirect access to the MDIO Manageable Device (MMD) registers. Refer to Section 4.3, "MDIO Manageable Device (MMD) Registers" for additional details.
LAN8740A/LAN8740Ai 4.2.11 MMD ACCESS ADDRESS/DATA REGISTER Index (In Decimal): 14 Size: 16 bits This register in conjunction with the MMD Access Control Register provides indirect access to the MDIO Manageable Device (MMD) registers. Refer to Section 4.3, "MDIO Manageable Device (MMD) Registers" for additional details.
LAN8740A/LAN8740Ai 4.2.12 EDPD NLP/CROSSOVER TIME/EEE CONFIGURATION REGISTER Index (In Decimal): 16 Size: 16 bits Bits Description Type Default 15 EDPD TX NLP Enable When in Energy Detect Power-Down (EDPD) mode (EDPWRDOWN = 1), this bit enables the transmission of single TX NLPs at the interval defined by the EDPD TX NLP Interval Timer Select field.
LAN8740A/LAN8740Ai 4.2.13 MODE CONTROL/STATUS REGISTER Index (In Decimal): Bits 15:14 13 9 8:7 6 5:2 Size: 16 bits Description Type Default RESERVED RO - EDPWRDOWN Enable the Energy Detect Power-Down (EDPD) mode: 0 = Energy Detect Power-Down is disabled. 1 = Energy Detect Power-Down is enabled. R/W 0b RESERVED RO - FARLOOPBACK Enables far loopback mode (i.e., all the received packets are sent back simultaneously (in 100BASE-TX only)). This bit is only active in RMII mode.
LAN8740A/LAN8740Ai 4.2.14 SPECIAL MODES REGISTER Index (In Decimal): Bits 18 Size: 16 bits Description Type Default 15 RESERVED RO - 14 MIIMODE Reflects the mode of the digital interface: 0 = MII mode 1 = RMII mode RO (see Note 1) 13:8 RESERVED RO - 7:5 MODE Transceiver mode of operation. Refer to Section 3.7.2, "MODE[2:0]: Mode Configuration" for additional details. R/W NASR (see Note 2) 4:0 PHYAD PHY Address.
LAN8740A/LAN8740Ai 4.2.15 TDR PATTERNS/DELAY CONTROL REGISTER Index (In Decimal): 24 Size: 16 bits Bits Description Type Default 15 TDR Delay In 0 = Line break time is 2 ms. 1 = The device uses TDR Line Break Counter to increase the line break time before starting TDR. R/W NASR 0b 14:12 TDR Line Break Counter When TDR Delay In is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds.
LAN8740A/LAN8740Ai 4.2.
LAN8740A/LAN8740Ai 4.2.17 SYMBOL ERROR COUNTER REGISTER Index (In Decimal): 26 Size: 16 bits Bits Description Type Default 15:0 Symbol Error Counter (SYM_ERR_CNT) This 100BASE-TX receiver-based error counter increments when an invalid code symbol is received, including IDLE symbols. The counter is incremented only once per packet, even when the received packet contains more than one symbol error. This field counts up to 65,536 and rolls over to 0 if incremented beyond it’s maximum value.
LAN8740A/LAN8740Ai 4.2.18 SPECIAL CONTROL/STATUS INDICATIONS REGISTER Index (In Decimal): Bits 27 Size: Description 15 AMDIXCTRL HP Auto-MDIX control: 0 = Enable Auto-MDIX 1 = Disable Auto-MDIX (use 27.
LAN8740A/LAN8740Ai 4.2.19 CABLE LENGTH REGISTER Index (In Decimal): Bits 15:12 Size: 16 bits Description Cable Length (CBLN) This four bit value indicates the cable length. Refer to Section 3.8.11.2, "Matched Cable Diagnostics" for additional information on the usage of this field. Note: 11:0 28 Default RO 0000b RO - This field indicates cable length for 100BASE-TX linked devices that do not have an open/short on the cable.
LAN8740A/LAN8740Ai 4.2.
LAN8740A/LAN8740Ai 4.2.21 INTERRUPT MASK REGISTER Index (In Decimal): Bits 30 Size: 16 bits Description Type Default 15:9 RESERVED RO - 8:1 Mask Bits These bits mask the corresponding interrupts in the Interrupt Source Flag Register. 0 = Interrupt source is masked. 1 = Interrupt source is enabled. R/W 00000000b RESERVED RO - 0 DS00001987A-page 80 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.2.22 PHY SPECIAL CONTROL/STATUS REGISTER Index (In Decimal): 31 Bits 15:13 12 11:7 Size: 16 bits Description Type Default RESERVED RO - Autodone Auto-negotiation done indication: 0 = Auto-negotiation is not done or disabled (or not active). 1 = Auto-negotiation is done. RO 0b RESERVED RO - 6 Enable 4B5B 0 = Bypass encoder/decoder 1 = Enable 4B5B encoding/decoding. MAC interface must be configured in MII mode.
LAN8740A/LAN8740Ai 4.3 MDIO Manageable Device (MMD) Registers The device MMD registers adhere to the IEEE 802.3-2008 45.2 MDIO Interface Registers specification. The MMD registers are not memory mapped. These registers are accessed indirectly via the MMD Access Control Register and MMD Access Address/Data Register. The supported MMD device addresses are 3 (PCS), 7 (Auto-Negotiation), and 30 (Vendor Specific). Table 4-3, "MMD Registers" details the supported registers within each MMD device.
LAN8740A/LAN8740Ai To read or write an MMD register, the following procedure must be observed: 1. 2. 3. 4. Write the MMD Access Control Register with 00b (address) for the MMD Function field and the desired MMD device (3 for PCS, 7 for Auto-Negotiation) for the MMD Device Address (DEVAD) field. Write the MMD Access Address/Data Register with the 16-bit address of the desired MMD register to read/write within the previously selected MMD device (PCS or Auto-Negotiation).
LAN8740A/LAN8740Ai 4.3.1 PCS CONTROL 1 REGISTER Index (In Decimal): Bits 15:11 10 Size: Description 16 bits Type Default RESERVED RO - Clock Stop Enable 0 = The PHY cannot stop the clock during Low Power Idle (LPI). 1 = The PHY may stop the clock during LPI. R/W 0b RO - Note: 9:0 3.0 The device does not support this mode. RESERVED DS00001987A-page 84 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.2 PCS STATUS 1 REGISTER Index (In Decimal): Bits 15:12 3.1 Size: Description RESERVED 16 bits Type Default RO - 11 TX LPI Received 0 = TX PCS has not received LPI. 1 = TX PCS has received LPI. RO/LH 0b 10 RX LPI Received 0 = RX PCS has not received LPI. 1 = RX PCS has received LPI. RO/LH 0b 9 TX LPI Indication 0 = TX PCS is not currently receiving LPI. 1 = TX PCS is currently receiving LPI. RO 0b 8 RX LPI Indication 0 = RX PCS is not currently receiving LPI.
LAN8740A/LAN8740Ai 4.3.3 PCS MMD DEVICES PRESENT 1 REGISTER Index (In Decimal): 3.
LAN8740A/LAN8740Ai 4.3.4 PCS MMD DEVICES PRESENT 2 REGISTER Index (In Decimal): Bits 3.
LAN8740A/LAN8740Ai 4.3.5 EEE CAPABILITY REGISTER Index (In Decimal): Bits 15:7 6 Description Size: 16 bits Type Default RESERVED RO - 10GBASE-KR EEE 0 = EEE is not supported for 10GBASE-KR. 1 = EEE is supported for 10GBASE-KR. RO 0b RO 0b RO 0b RO 0b RO 0b Note: 5 3.20 The device does not support this mode. 10GBASE-KX4 EEE 0 = EEE is not supported for 10GBASE-KX4. 1 = EEE is supported for 10GBASE-KX4. Note: The device does not support this mode.
LAN8740A/LAN8740Ai 4.3.6 EEE WAKE ERROR REGISTER Index (In Decimal): Bits 15:0 3.22 Size: 16 bits Description EEE Wake Error Counter This counter is cleared to zeros on read and is held to all ones on overflow. 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.7 WAKEUP CONTROL AND STATUS REGISTER (WUCSR) Index (In Decimal): Bits 15 14:13 Default Interface Disable 0 = MII/RMII interface enabled 1 = MII/RMII interface disabled. Outputs driven to a low level and inputs ignored. R/W NASR 0b LED1 Function Select 00 = LED1 functions as Link/Activity. 01 = LED1 functions as nINT. 10 = LED1 functions as nPME. 11 = LED1 functions as Link Speed. R/W NASR 0b R/W NASR 0b R/W NASR 0b R/W NASR 0b R/W/ NASR 0b Refer to Section 3.8.
LAN8740A/LAN8740Ai Bits Description Type Default 3 Perfect DA Wakeup Enable (PFDA_EN) When set, remote wakeup mode is enabled and the MAC is capable of waking up on receipt of a frame with a destination address that matches the physical address of the device. The physical address is stored in the MAC Receive Address A Register (RX_ADDRA), MAC Receive Address B Register (RX_ADDRB) and MAC Receive Address C Register (RX_ADDRC).
LAN8740A/LAN8740Ai 4.3.8 WAKEUP FILTER CONFIGURATION REGISTER A (WUF_CFGA) Index (In Decimal): Bits 3.32785 Size: 16 bits Description Type Default 15 Filter Enable 0 = Filter disabled 1 = Filter enabled R/W/ NASR 0b 14 Filter Triggered 0 = Filter not triggered 1 = Filter triggered R/WC/ NASR 0b 13:11 RO - 10 RESERVED Address Match Enable When set, the destination address must match the programmed address. When cleared, any unicast packet is accepted. Refer to Section 3.8.4.
LAN8740A/LAN8740Ai 4.3.9 WAKEUP FILTER CONFIGURATION REGISTER B (WUF_CFGB) Index (In Decimal): 3.32786 Size: 16 bits Bits Description Type Default 15:0 Filter CRC-16 This field specifies the expected 16-bit CRC value for the filter that should be obtained by using the pattern offset and the byte mask programmed for the filter. This value is compared against the CRC calculated on the incoming frame, and a match indicates the reception of a Wakeup Frame.
LAN8740A/LAN8740Ai 4.3.10 WAKEUP FILTER BYTE MASK REGISTERS (WUF_MASK) Index (In Decimal): Bits 15:0 3.32803 Size: Bits Size: Wakeup Filter Byte Mask [79:64] Bits 3.32805 Size: Wakeup Filter Byte Mask [63:48] Bits 3.32806 Size: Wakeup Filter Byte Mask [47:32] DS00001987A-page 94 3.
LAN8740A/LAN8740Ai Bits 15:0 Description Wakeup Filter Byte Mask [31:16] Index (In Decimal): Bits 15:0 3.32808 Description Wakeup Filter Byte Mask [15:0] 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.11 MAC RECEIVE ADDRESS A REGISTER (RX_ADDRA) Index (In Decimal): Bits 15:0 Note: 3.32865 Description Physical Address [47:32] Size: 16 bits Type Default R/W/ NASR FFFFh The MAC address must be loaded into the RX_ADDRA, RX_ADDRB, and RX_ADDRC registers in the proper byte order.
LAN8740A/LAN8740Ai 4.3.12 MAC RECEIVE ADDRESS B REGISTER (RX_ADDRB) Index (In Decimal): Bits 15:0 Note: 3.32866 Description Physical Address [31:16] Size: 16 bits Type Default R/W/ NASR FFFFh The MAC address must be loaded into the RX_ADDRA, RX_ADDRB, and RX_ADDRC registers in the proper byte order. For example, a MAC address of 12:34:56:78:9A:BC should be loaded into these registers as follows: RX_ADDRA = BC9Ah RX_ADDRB = 7856h RX_ADDRC = 3412h 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.13 MAC RECEIVE ADDRESS C REGISTER (RX_ADDRC) Index (In Decimal): Bits 15:0 Note: 3.32867 Description Physical Address [15:0] Size: 16 bits Type Default R/W/ NASR FFFFh The MAC address must be loaded into the RX_ADDRA, RX_ADDRB, and RX_ADDRC registers in the proper byte order.
LAN8740A/LAN8740Ai 4.3.14 MISCELLANEOUS CONFIGURATION REGISTER (MCFGR) Index (In Decimal): Bits 15:0 3.32868 Size: 16 bits Description nPME Assert Delay This register controls the delay of nPME de-assertion time when the nPME Self Clear bit of the Wakeup Control and Status Register (WUCSR) is set. Each count is equivalent to a 20 µs delay. The delay max is 1.31 seconds. Time = (register value + 1) x 20 µs. 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.15 AUTO-NEGOTIATION MMD DEVICES PRESENT 1 REGISTER Index (In Decimal): 7.
LAN8740A/LAN8740Ai 4.3.16 AUTO-NEGOTIATION MMD DEVICES PRESENT 2 REGISTER Index (In Decimal): Bits 7.
LAN8740A/LAN8740Ai 4.3.17 EEE ADVERTISEMENT REGISTER Index (In Decimal): Bits 15:2 7.60 Size: Description RESERVED 1 100BASE-TX EEE 0 = Do not advertise EEE capability for 100BASE-TX. 1 = Advertise EEE capability for 100BASE-TX. 0 RESERVED 16 bits Type Default RO - (see Note 1) (see Note 2) RO - Note 1: This bit is read/write (R/W). However, the user must not set this bit if EEE is disabled.
LAN8740A/LAN8740Ai 4.3.18 EEE LINK PARTNER ADVERTISEMENT REGISTER Index (In Decimal): Bits 15:7 6 Size: 16 bits Description Type Default RESERVED RO - 10GBASE-KR EEE 0 = Link partner does not advertise EEE capability for 10GBASE-KR. 1 = Link partner advertises EEE capability for 10GBASE-KR. RO 0b RO 0b RO 0b RO 0b RO 0b Note: 5 7.61 This device does not support this mode. 10GBASE-KX4 EEE 0 = Link partner does not advertise EEE capability for 10GBASE-KX4.
LAN8740A/LAN8740Ai 4.3.19 VENDOR SPECIFIC MMD 1 DEVICE ID 1 REGISTER Index (In Decimal): Bits 15:0 30.2 Description RESERVED DS00001987A-page 104 Size: 16 bits Type Default RO 0000h 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.20 VENDOR SPECIFIC MMD 1 DEVICE ID 2 REGISTER Index (In Decimal): Bits 15:0 30.3 Description RESERVED 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.21 VENDOR SPECIFIC 1 MMD DEVICES PRESENT 1 REGISTER Index (In Decimal): 30.
LAN8740A/LAN8740Ai 4.3.22 VENDOR SPECIFIC 1 MMD DEVICES PRESENT 2 REGISTER Index (In Decimal): Bits 30.
LAN8740A/LAN8740Ai 4.3.23 VENDOR SPECIFIC MMD 1 STATUS REGISTER Index (In Decimal): Bits 30.8 Description 15:14 Device Present 00 = No device responding at this address 01 = No device responding at this address 10 = Device responding at this address 11 = No device responding at this address 13:0 RESERVED DS00001987A-page 108 Size: 16 bits Type Default 10b RO - 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.24 TDR MATCH THRESHOLD REGISTER Index (In Decimal): Bits 15:10 30.11 Description Size: 16 bits Type Default RESERVED RO - 9:5 TDR Match High Threshold Sets the upper threshold to detect match cable. R/W 5’h12 (see Note 1) 4:0 TDR Match Low Threshold Sets the lower threshold to detect match cable. R/W 5’h09 (see Note 1) Note 1: Software reset places the default values of this register into an indeterminate state.
LAN8740A/LAN8740Ai 4.3.25 TDR SHORT/OPEN THRESHOLD REGISTER Index (In Decimal): Bits 15:10 30.12 Description Size: 16 bits Type Default RESERVED RO - 9:5 TDR Short Low Threshold Sets the lower threshold to detect short cable. R/W 5’h09 (see Note 1) 4:0 TDR Open High Threshold Sets the upper threshold to detect open cable. R/W 5’h12 (see Note 1) Note 1: Software reset places the default values of this register into an indeterminate state.
LAN8740A/LAN8740Ai 4.3.26 VENDOR SPECIFIC MMD 1 PACKAGE ID 1 REGISTER Index (In Decimal): Bits 15:0 30.14 Description RESERVED 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 4.3.27 VENDOR SPECIFIC MMD 1 PACKAGE ID 2 REGISTER Index (In Decimal): Bits 15:0 30.15 Description RESERVED DS00001987A-page 112 Size: 16 bits Type Default RO 0000h 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VDDIO, VDD1A, VDD2A) (see Note 1).......................................................................... -0.5 V to +3.6 V Digital Core Supply Voltage (VDDCR) (see Note 1) ................................................................................ -0.5 V to +1.5 V Ethernet Magnetics Supply Voltage .........................................................................................................
LAN8740A/LAN8740Ai 5.4 Power Consumption This section details the device power measurements taken over various operating conditions. Unless otherwise noted, all measurements were taken with power supplies at nominal values (VDDIO, VDD1A, VDD2A = 3.3 V, VDDCR = 1.2 V). See Section 3.8.3, "Power-Down Modes" for a description of the power down modes. 5.4.1 REGULATOR DISABLED TABLE 5-2: CURRENT CONSUMPTION AND POWER DISSIPATION (REG. DISABLED) Power Pin Group 3.3 V Device Current (mA) 1.
LAN8740A/LAN8740Ai 5.5 DC Specifications Table 5-4 details the non-variable I/O buffer characteristics. These buffer types do not support variable voltage operation. Table 5-5 details the variable voltage I/O buffer characteristics. Typical values are provided for 1.8 V, 2.5 V, and 3.3 V VDDIO cases. TABLE 5-4: NON-VARIABLE I/O BUFFER CHARACTERISTICS Parameter Symbol Min. Low Input Level VILI -0.3 High Input Level VIHI Negative-Going Threshold VILT 1.
LAN8740A/LAN8740Ai TABLE 5-5: VARIABLE I/O BUFFER CHARACTERISTICS Parameter 1.8 V Typ. 2.5 V Typ. Symbol Min. Low Input Level VILI -0.3 High Input Level VIHI Neg-Going Threshold VILT 0.64 0.83 1.15 Pos-Going Threshold VIHT 0.81 0.99 Schmitt Trigger Hysteresis (VIHT - VILT) VHYS 102 158 Input Leakage (VIN = VSS or VDDIO) IIH -10 Input Capacitance 3.3 V Typ. Max. Unit Note VIS Type Input Buffer V 3.6 V 1.41 1.76 V Schmitt trigger 1.29 1.65 1.
LAN8740A/LAN8740Ai 5.6 AC Specifications This section details the various AC timing specifications of the device. 5.6.1 EQUIVALENT TEST LOAD Output timing specifications assume a 25 pF equivalent test load, unless otherwise noted, as illustrated in Figure 5-1 below. FIGURE 5-1: OUTPUT EQUIVALENT TEST LOAD OUTPUT 25 pF 2013-2015 Microchip Technology Inc.
LAN8740A/LAN8740Ai 5.6.2 POWER-ON nRST & CONFIGURATION STRAP TIMING This diagram illustrates the nRST reset and configuration strap timing requirements in relation to power-on. A hardware reset (nRST assertion) is required following power-up. For proper operation, nRST must be asserted for no less than trstia. The nRST pin can be asserted at any time, but must not be deasserted before tpurstd after all external power supplies have reached operational levels.
LAN8740A/LAN8740Ai 5.6.3 MII INTERFACE TIMING This section specifies the MII interface transmit and receive timing. Please refer to Section 3.4.1, "MII" for additional details. FIGURE 5-3: MII RECEIVE TIMING tclkp tclkh RXCLK (OUTPUT) tclkl tval tval tinvld RXD[3:0] (OUTPUTS) tinvld tval RXDV, RXER (OUTPUTS) TABLE 5-9: Symbol MII RECEIVE TIMING VALUES Description Min. Typ. Max. Note tclkp RXCLK period tclkh RXCLK high time tclkp * 0.4 tclkp * 0.
LAN8740A/LAN8740Ai FIGURE 5-4: MII TRANSMIT TIMING tclkp tclkh TXCLK (OUTPUT) tclkl tsu thold tsu thold thold TXD[3:0] (INPUTS) thold tsu TXEN, TXER (INPUTS) TABLE 5-10: MII TRANSMIT TIMING VALUES Symbol Description Min. Typ. Max. Note tclkp TXCLK period tclkh TXCLK high time tclkp * 0.4 tclkp * 0.6 ns tclkl TXCLK low time tclkp * 0.4 tclkp * 0.6 ns tsu TXD[3:0], TXEN, TXER setup time to rising edge of TXCLK 12.
LAN8740A/LAN8740Ai 5.6.3.1 100 Mbps Internal Loopback MII Timing FIGURE 5-5: 100 MBPS INTERNAL LOOPBACK MII TIMING TXCLK (OUTPUT) TXEN (INPUT) t1 RXDV (OUTPUT) RXD[3:0] (OUTPUTS) TABLE 5-11: Symbol t1 Note: 100 MBPS INTERNAL LOOPBACK MII TIMING VALUES Description TXCLK rising edge after TXEN assertion to RXDV assertion (100 Mbps internal loopback MII mode) Min. Typ. Max.
LAN8740A/LAN8740Ai 5.6.4 RMII INTERFACE TIMING This section specifies the RMII interface transmit and receive timing. Note: The CRS_DV pin performs both carrier sense and data valid functions. CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode.
LAN8740A/LAN8740Ai 5.6.4.1 RMII CLKIN Requirements TABLE 5-13: RMII CLKIN (REF_CLK) TIMING VALUES Parameter Min. CLKIN frequency Typ. Max. 50 CLKIN Frequency Drift CLKIN Duty Cycle 5.6.5 Note MHz ±50 ppm 60 % 150 ps 40 CLKIN Jitter Unit p-p – not RMS SMI TIMING This section specifies the SMI timing of the device. Please refer to Section 3.5, "Serial Management Interface (SMI)" for additional details.
LAN8740A/LAN8740Ai 5.7 Clock Circuit The device can accept either a 25 MHz crystal or a 25 MHz single-ended clock oscillator (±50ppm) input. If the singleended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3 V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
LAN8740A/LAN8740Ai 3: The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as ±50 ppm. 4: 0°C for commercial version, -40°C for industrial version 5: +70°C for commercial version, +85°C for industrial version 6: This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The XTAL1/CLKIN pin, XTAL2 pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors.
LAN8740A/LAN8740Ai Note 1: The maximum allowable values for frequency tolerance and frequency stability are application dependent. Since any particular application must meet the IEEE ±50 ppm Total PPM Budget, the combination of these two values must be approximately ±45 ppm (allowing for aging). 2: Frequency Deviation Over Time is also referred to as Aging. 3: The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as ±50 ppm.
LAN8740A/LAN8740Ai 6.0 PACKAGE OUTLINE 32-Lead Very Thin Plastic Quad Flat, No Lead Package (MQ) - 5x5x0.9 mm Body [VQFN] SMSC LEGACY SQFN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N 1 2 NOTE 1 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C (A3) A1 C A SEATING PLANE 32X SIDE VIEW 0.10 0.08 C C A B D2 0.10 C A B E2 e 2 2 1 NOTE 1 32X K N 32X L 32X b 0.10 0.
LAN8740A/LAN8740Ai 32-Lead Very Thin Plastic Quad Flat, No Lead Package (MQ) - 5x5x0.9 mm Body [VQFN] SMSC LEGACY SQFN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width Overall Length D D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.
LAN8740A/LAN8740Ai 32-Lead Very Thin Plastic Quad Flat, No Lead Package (MQ) - 5x5mm Body [VQFN] SMSC LEGACY SQFN Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
LAN8740A/LAN8740Ai APPENDIX A: REVISION HISTORY REVISION LEVEL & DATE Revision A (09-07-15) Rev. 1.1 (05-10-13) SECTION/FIGURE/ENTRY CORRECTION Replaces the previous SMSC version Rev. 1.
LAN8740A/LAN8740Ai REVISION LEVEL & DATE Rev. 1.1 (05-10-13) SECTION/FIGURE/ENTRY CORRECTION Section 4.3, "MDIO Manageable Device Added additional vendor specific MMD register (MMD) Registers" descriptions Section 4.3.11, "MAC Receive Address Added note A Register (RX_ADDRA)" Section 4.3.12, "MAC Receive Address Added note B Register (RX_ADDRB)" Section 4.3.13, "MAC Receive Address Added note C Register (RX_ADDRC)" , "," on page 113 Removed section “Power Sequence Timing” Section 5.
LAN8740A/LAN8740Ai NOTES: DS00001987A-page 132 2013-2015 Microchip Technology Inc.
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LAN8740A/LAN8740Ai PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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