Datasheet

 2016 Microchip Technology Inc. DS00002165B-page 75
LAN8710A/LAN8710AI
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1: REVISION HISTORY
Revision Section/Figure/Entry Correction
Rev B. (07-15-16) Section 5.1, "Absolute Maxi-
mum Ratings*," on page 54
Update to Positive voltage on XTAL1/CLKIN, with
respe
ct to ground.
Table 5-2, “Non-Variable I/O
Buffer Characteristics,” on
page 56
Update to min/max values for the last row, ICLK
T
ype Buffer (XTAL1 Input) - High Input Level.
Rev. A (06-24-16) All Document converted to Microchip look and feel.
Rep
laces SMSC Rev. 1.4 (08-23-12).
Section 5.2, "Operating Con-
ditions**," on page 54
Increased VDDCR operational limits from “+1.14V
to
+1.26V” to “+1.08V to +1.32V”
Section 5.6, "Clock Circuit,"
on page 65
Added new 100uW crystal specifications and circuit
dia
gram. The section is now split into two subsec-
tions, one for 300uW crystals and the other for
100uW cryst
als.
Section 6.0, "Package Infor-
mation," on page 68
Added new subsections to include SQFN package
information.
Section , "Product Identifica-
tion System," on page 77
Updated ordering codes with sawn SQFN package
options.
Rev. 1.4
(08-23-12)
Section 4.2.2, Basic Status
Register
Updated definitions of bits 10:8.
Section 4.2.14, "PHY Spe-
cial Control/Status Regis-
ter," on page 53
Updated bit 6 definition.
Cover Ordering information modified.
Rev. 1.3
(04-20-11)
Cover Added copper bond wire ordering codes to
LAN8710 ordering codes
Table 4.2.9, “Special Modes
Register,” on page 50
Updated MIIMODE bit description and added note:
“When writing to this register the default value of
this bit must always be written back.”
Section 3.7.3, "RMIISEL:
MII/RMII Mode Configura-
tion," on page 31
Updated second paragraph to:
“When the nRST pin is deasserted, the MIIMODE
bit of the Special Modes Register is loaded accord-
ing to the
RMIISEL configuration strap. The mode
is reflected in the MIIMODE bit of the Special
Modes Register
.”
Section 3.8.9.2, "Far Loop-
back," on page 36
Updated section to defeature information about
register control of the MII/RMII mode.
Rev. 1.2 (11-10-10) Section 5.5.5, "RMII Inter-
face Timing," on page 63
Updated diagrams and tables to include RXER.