Datasheet

FIGURE 5-5: MII TRANSMIT TIMING
TXCLK
t
su
TXD[3:0]
TXEN
t
clkh
t
clkl
t
clkp
t
hold
t
su
t
hold
t
hold
t
su
t
hold
TABLE 5-8: MII TRANSMIT TIMING VALUES
SYMBOL DESCRIPTION MIN MAX UNITS NOTES
t
clkp
TXCLK period Note 5-23 — ns —
t
clkh
TXCLK high time t
clkp
*0.4 t
clkp
*0.6 ns —
t
clkl
TXCLK low time t
clkp
*0.4 t
clkp
*0.6 ns —
t
su
TXD[3:0], TXEN setup time to rising edge of
TXCLK
12.0 — ns Note 5-24
t
hold
TXD[3:0], TXEN hold time after rising edge of
TXCLK
0 — ns Note 5-24
LAN8710A/LAN8710AI
DS00002164B-page 62  2016 Microchip Technology Inc.
Note 5-23 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5-24 T
iming was designed for system load between 10 pf and 25 pf.