Datasheet

FIGURE 5-4: MII RECEIVE TIMING
RXCLK
RXD[3:0]
RXDV
t
clkh
t
clkl
t
clkp
t
val
t
hold
t
val
t
val
t
hold
Table 1.1 MII Receive Timing Values
SYMBOL DESCRIPTION MIN MAX UNITS NOTES
t
clkp
RXCLK period Note 5-21 — ns
t
clkh
RXCLK high time t
clkp
*0.4 t
clkp
*0.6 ns
t
clkl
RXCLK low time t
clkp
*0.4 t
clkp
*0.6 ns
t
val
RXD[3:0], RXDV output valid from rising edge of
RXCLK
28.0 ns Note 5-22
t
hold
RXD[3:0], RXDV output hold from rising edge of
RXCLK
10.0 — ns Note 5-22
 2016 Microchip Technology Inc. DS00002164B-page 61
LAN8710A/LAN8710AI
Note 5-21 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
Note 5-22 T
iming was designed for system load between 10 pf and 25 pf.