Datasheet

FIGURE 5-3: POWER-ON NRST & CONFIGURATION STRAP TIMING
t
css
nRST
Configuration Strap
Pins Input
t
rstia
t
csh
Configuration Strap
Pins Output Drive
t
odad
All External
Power Supplies
t
purstd
80%
t
purstv
t
otaa
TABLE 5-7: POWER-ON NRST & CONFIGURATION STRAP TIMING VALUES
symbol DESCRIPTION min typ max units
t
purstd
External power supplies at 80% to nRST deassertion 25 — — mS
t
purstv
External power supplies at 80% to nRST valid 0 — — nS
t
rstia
nRST input assertion time 100 — — S
t
css
Configuration strap pins setup to nRST deassertion 200 — — nS
t
csh
Configuration strap pins hold after nRST deassertion 1 — — nS
t
otaa
Output tri-state after nRST assertion — 50 nS
t
odad
Output drive after nRST deassertion 2 — 800
(Note 5-
20)
nS
LAN8710A/LAN8710AI
DS00002164B-page 60  2016 Microchip Technology Inc.
Note 5-18 nRST deassertion must be monotonic.
Note 5-19 De
vice configuration straps are latched as a result of nRST assertion. Refer to Section 3.7,
Configuration Straps for details. Configuration straps must only be pulled high or low and must not
be driven as inputs.
Note 5-20 20 clock cycles for 25MHz, or 40
clock cycles for 50MHz.
5.5.4 MII INTERFACE TIMING
This section specifies the MII interface transmit and receive timing. Please refer to Section 3.4.1, MII
for additional details.