Datasheet

FIGURE 1-1: SYSTEM BLOCK DIAGRAM
LAN8710A/
LAN8710Ai
10/100
Ethernet
MAC
MII/
RMII
Mode LED
Transformer
Crystal or
Clock
Oscillator
MDI
RJ45
FIGURE 1-2: ARCHITECTURAL OVERVIEW
RMII/MII Logic
Interrupt
Generator
LEDs
PLL
Receiver
DSP System:
Clock
Data Recovery
Equalizer
Squeltch
& Filters
Analog-to-
Digital
10M RX
Logic
100M RX
Logic
100M PLL
10M PLL
Transmitter
10M
Transmitter
100M
Transmitter
10M TX
Logic
100M TX
Logic
Central Bias
PHY Address
Latches
LAN8710A/LAN8710Ai
RBIAS
LED1
nINT
XTAL2
XTAL1/CLKIN
LED2
Management
Control
Mode Control
Reset Control
MDIX
Control
HP Auto-MDIX
RXP/RXN
TXP/TXN
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
Auto-
Negotiation
RMIISEL
nRST
MODE[0:2]
SMI
PHYAD[0:2]
 2016 Microchip Technology Inc. DS00002164B-page 5
LAN8710A/LAN8710AI