Datasheet

ManualsBrandsMicrochip ManualsIntegrated Circuits (ICs)Ethernet Transceiver QFN 54mA MII / RMII

TABLE 3-6: MODE[2:0] BUS

MODE[2:0] Mode Definitions

Default Register Bit Values

[13,12,10,8] [8,7,6,5]

000 10Base-T Half Duplex. Auto-negotiation disabled. 0000 N/A

001 10Base-T Full Duplex. Auto-negotiation disabled. 0001 N/A

010 100Base-TX Half Duplex. Auto-negotiation dis-

abled.

CRS is active during Transmit & Receive.

1000 N/A

011 100Base-TX Full Duplex. Auto-negotiation disabled.

CRS is active during Receive.

1001 N/A

100 100Base-TX Half Duplex is advertised. Auto-negoti-

ation enabled.

CRS is active during Transmit & Receive.

1100 0100

101 Repeater mode. Auto-negotiation enabled.

100

Base-TX Half Duplex is advertised.

CRS is active during Receive.

1100 0100

110 Power Down mode. In this mode the transceiver will

wake-up in Power-Down mode. The transceiver

cannot be used when the MODE[2:0] bits are set to

this mode. To exit this mode, the MODE bits in Reg-

ister 18.7:5(see Section 4.2.9, "Special Modes Reg-

ister," on page 50) must be configured to some

other value and a soft reset must be issued.

N/A N/A

111 All capable. Auto-negotiation enabled. X10X 1111

 2016 Microchip Technology Inc. DS00002164B-page 31

LAN8710A/LAN8710AI

The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3-7.

TABLE 3-7: PIN NAMES FOR MODE BITS

MODE Bit Pin Name

MODE[0] RXD0/

MODE0

MODE[1] RXD1/MODE1

MODE[2] COL/CRS_DV/MODE2

3.7.3 RMIISEL: MII/RMII MODE CONFIGURATION

MII or RMII mode selection is latched on the rising edge of the internal reset (nRST) based on the strapping of the RMI-

ISEL configuration strap. The default mode is MII (via the internal pull-down resistor). To select RMII mode, pull the RMI-

ISEL configuration strap high with an external resistor to VDDIO.

When the nRST pin is deasserted, the MIIMODE bit of the Special Modes Register is loaded according to the

RMIISEL

configuration strap. The mode is reflected in the MIIMODE bit of the Special Modes Register.

Refer to Section 3.4, "MAC Interface," on page 24 for additional information on MII and RMII modes.