Datasheet

LAN8710A/LAN8710AI
DS00002164B-page 30  2016 Microchip Technology Inc.
The device’s SMI address may be configured using hardware configuration to any value between 0 and 7. The user can
configure the PHY address using Software Configuration if an address greater than 7 is required. The PHY address can
be written (after SMI communication at some address is established) using the PHYAD bits of the Special Modes Reg-
ister. The
PHYAD[2:0] configuration straps are multiplexed with other signals as shown in Table 3-5.
TABLE 3-5: PIN NAMES FOR ADDRESS BITS
Address Bit Pin Name
PHYAD[0] RXER/RXD4/
PHYAD0
PHYAD[1] RXCLK/PHYAD1
PHYAD[2] RXD3/PHYAD2
3.7.2 MODE[2:0]: MODE CONFIGURATION
The MODE[2:0] configuration straps control the configuration of the 10/100 digital block. When the nRST pin is deas-
serted, the register bit values are loaded according to the MODE[2:0] configuration straps. The 10/100 digital block is
then configured by the register bit values. When a soft reset occurs via the Soft Reset bit of the Basic Control Register,
the configuration of the 10/100 digit
al block is controlled by the register bit values and the MODE[2:0] configuration
straps have no affect.
The device’s mode may be configured using the h
ardware configuration straps as summarized in Table 3-6. The user
may configure the transceiver mode
by writing the SMI registers.