Datasheet

 2016 Microchip Technology Inc. DS00002164B-page 29
LAN8710A/LAN8710AI
For example, setting the INT7 bit in the Interrupt Mask Register will enable the ENERGYON interrupt. After a cable is
plugged in, the ENERGYON bit in the Mode Control/Status Register goes active and nINT will be asserted low. To de-
assert the nINT interrupt output, either clear the ENERGYON bit in the Mode Control/Status Register by removing the
cable and then writing a ‘1’ to the INT7 bit in the Interrupt Mask Register,
OR clear the INT7 mask (bit 7 of the Interrupt
Mask Register).
TABLE 3-4: ALTERNATIVE INTERRUPT SYSTEM MANAGEMENT TABLE
Mask Interrupt Source Flag Interrupt Source
Event to
Ass
ert nINT
Condition to
De-Assert
Bit to
Cl
ear
nINT
30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 17.1 low 29.7
30.6 29.6 Auto-Negotiation
com
plete
1.5 Auto-Negotiate
Complete
Rising 1.5 1.5 low 29.6
30.5 29.5 Remote Fault
De
tected
1.4 Remote Fault Rising 1.4 1.4 low 29.5
30.4 29.4 Link Down 1.2 Link Status Falling 1.2 1.2 high 29.4
30.3 29.3 Auto-Negotiation
LP Acknowledge
5.14 Acknowledge Rising 5.14 5.14 low 29.3
30.2 29.2 Parallel Detec-
tion Fault
6.4 Parallel Detec-
tion Fault
Rising 6.4 6.4 low 29.2
30.1 29.1 Auto-Negotiation
Pa
ge Received
6.1 Page Received Rising 6.1 6.1 low 29.1
Note: Th
e ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-
sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no
signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.
3.7 Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined values. Config-
uration straps are latched upon Power-On Reset (POR) and pin
reset (nRST). Configuration straps include internal
resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected
to a load, an external pull-up or pull-down resistor should be used to augment the internal resistor to ensure that it
reaches the required voltage level prior to latching. The internal resistor can also be overridden by the addition of an
external resistor.
Note 3-4 The system
designer must guarantee that configuration strap pins meet the timing requirements
specified in Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page 59. If
configuration strap pins are not at the correct
voltage level prior to being latched, the device may
capture incorrect strap values.
Note 3-5 W
hen externally pulling configuration straps high, the strap should be tied to VDDIO, except for
REGOFF and nINTSEL which should be tied to VDD2A.
3.7.1 PHYAD[2:0]: PHY ADDRESS CONFIGURATION
The PHYAD[2:0] configuration straps are driven high or low to give each PHY a unique address. This address is latched
into an internal register at the end of a hardware reset (default = 000b). In a multi-transceiver application (such as a
repeater), the controller is able to manage each transceiver via the unique address. Each transceiver checks each man-
agement data frame for a matching address in the relevant bi
ts. When a match is recognized, the transceiver responds
to that particular frame. The PHY address is also used to seed the scrambler. In a multi-transceiver application, this
ensures that the scramblers are out of synchronization and disperses the electromagnetic radiation across the fre-
quency spectrum.