Datasheet

LAN8710A/LAN8710AI
DS00002164B-page 28  2016 Microchip Technology Inc.
3.6.1 PRIMARY INTERRUPT SYSTEM
The Primary interrupt system is the default interrupt mode (ALTINT bit of the Mode Control/Status Register is “0”). The
Primary interrupt system is always selected after power-up or
hard reset. In this mode, to set an interrupt, set the cor-
responding mask bit in the Interrupt Mask Register (see Table 3-3). Then when the event to assert nINT is true, the nINT
output will be asserted. When the corresponding event to deassert nINT is true, then the nINT will be de-asserted.
TABLE 3-3: INTERRUPT MANAGEMENT TABLE
Mask Interrupt Source Flag Interrupt Source
Event to Assert
nI
NT
Event to
De-Assert nINT
30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1
(Note 3-3)
Falling 17.1 or
Reading register 29
30.6 29.6 Auto-Negotiation
complete
1.5 Auto-Negotiate
Comple
te
Rising 1.5 Falling 1.5 or
Reading register 29
30.5 29.5 Remote Fault
Detected
1.4 Remote Fault Rising 1.4 Falling 1.4, or
Reading register 1 or
Reading register 29
30.4 29.4 Link Down 1.2 Link Status Falling 1.2 Reading register 1 or
Reading register 29
30.3 29.3 Auto-Negotiation
LP Ackn
owledge
5.14 Acknowledge Rising 5.14 Falling 5.14 or
Read register 29
30.2 29.2 Parallel Detection
Fa
ult
6.4 Parallel Detec-
tion Fault
Rising 6.4 Falling 6.4 or
Reading register 6, or
Reading register 29
or
Re-Auto Negotiate or
Link down
30.1 29.1 Auto-Negotiation
Page
Received
6.1 Page Received Rising 6.1 Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-Auto Negotiate, or
Link Down.
Note 3-3 If
the mask bit is enabled and nINT has been de-asserted while ENERGYON is still high, nINT will
assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is
unplugged. To prevent an unexpected assertion of nINT, the ENERGYON interrupt mask should
always be cleared as part of the ENERGYON interrupt service routine.
Note: Th
e ENERGYON bit in the Mode Control/Status Register is defaulted to a ‘1’ at the start of the signal acqui-
sition process, therefore the INT7 bit in the Interrupt Mask Register will also read as a ‘1’ at power-up. If no
signal is present, then both ENERGYON and INT7 will clear within a few milliseconds.
3.6.2 ALTERNATE INTERRUPT SYSTEM
The Alternate interrupt system is enabled by setting the ALTINT bit of the Mode Control/Status Register to “1”. In this
mode, to set an interrupt, set the corresponding bit of the in the Mask Register 30, (see Table 3-4). To Clear an interrupt,
either clear the corresponding bit in the Interrupt Mask Register to deassert the nINT output, or clear the interrupt
source, and write a ‘1’ to the corresponding Interrupt Source
Flag. Writing a ‘1’ to the Interrupt Source Flag will cause
the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If
the Condition to deassert is true, then the Interrupt Source Flag is cleared and nINT is also deasserted. If the Condition
to deassert is false, then the Interrupt Source Flag remains set, and the nINT remains asserted.