Datasheet

 2016 Microchip Technology Inc. DS00002164B-page 27
LAN8710A/LAN8710AI
3.5 Serial Management Interface (SMI)
The Serial Management Interface is used to control the device and obtain its status. This interface supports registers 0
through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers 16 to 31 allowed by the
specification. Non-supported registers (such as 7 to 15) will be read as hexadecimal “FFFF”. Device registers are
detailed in Section 4.0, "Register Descriptions," on page 43.
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is
an aperiodic clock provided by the
station management controller (SMC). MDIO is a bi-directional data SMI input/output signal that receives serial data
(commands) from the controller SMC and sends serial data (status) to the SMC. The minimum time between edges of
the MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutive
rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily
driven by the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. Th
e frame structure and timing of the data is shown
in Figure 3-5 and Figure 3-6. The timing relationships of the MDIO signals are further described in Section 5.5.6, "SMI
Timing," on page 64.
FIGURE 3-5:
MDC
MDIO
Read Cycle
...
32 1's 0110A4A3A2A1A0R4R3R2R1R0
D1
...
D15 D14 D0
Preamble
Start of
Frame
OP
Code
PHY Address Register Address
Turn
Around
Data
Data From Phy
Data To Phy
MDIO TIMING AND FRAME STRUCTURE - READ CYCLE
FIGURE 3-6:
MDC
MDIO
...
32 1's 0 1 10 A4A3A2A1A0R4R3R2R1R0
Write Cycle
D15 D14 D1 D0
...
DataPreamble
Start of
Frame
OP
Code
PHY Address Register Address
Turn
Around
Data To Phy
MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE
3.6 Interrupt Management
The device management interface supports an interrupt capability that is not a part of the IEEE 802.3 specification. This
interrupt capability generates an active low asynchronous interrupt signal on the nINT output whenever certain events
are detected as setup by the Interrupt Mask Register.
The device’s interrupt system provides two
modes, a Primary Interrupt mode and an Alternative interrupt mode. Both
systems will assert the nINT pin low when the corresponding mask bit is set. These modes differ only in how they de-
assert the nINT interrupt output. These modes are detailed in the following subsections.
Note: Th
e Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative
interrupt mode requires setup after a power-up or hard reset.