Datasheet

LAN8710A/LAN8710AI

DS00002164B-page 26  2016 Microchip Technology Inc.

3.4.2.2 Reference Clock (REF_CLK)

The RMII REF_CLK is a continuous clock that provides the timing reference for CRS_DV, RXD[1:0], TXEN, TXD[1:0]

and RXER. The device uses REF_CLK as the network clock such that no buffering is required on the transmit data path.

However, on the receive data path, the receiver recovers the clock from the incoming data stream, and the device uses

elasticity buffering to accommodate for differences between the recovered clock and the local REF_CLK.

3.4.2.3 MII vs. RMII Configuration

The device must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done

via the RMIISEL configuration strap. MII or RMII mode selection is configured based on the strapping of the RMIISEL

configuration strap as described in Section 3.7.3, "RMIISEL: MII/RMII Mode Configuration," on page 31.

Most of the MII and RMII pin

s are multiplexed. Table 3-2 describes the relationship of the related device pins to the MII

and RMII mode signal names.

TABLE 3-2: MII/RMII SIGNAL MAPPING

PIN Name MII Mode RMII Mode

TXD0 TXD0 TXD0

TXD1 TXD1 TXD1

TXEN TXEN TXEN

RXER/

RXD4/PHYAD0

RXER RXER

Note 3-2

COL/CRS_DV/MODE2 COL CRS_DV

RXD0/MODE0 RXD0 RXD0

RXD1/MODE1 RXD1 RXD1

TXD2 TXD2 Note 3-1

TXD3 TXD3 Note 3-1

nINT/TXER/TXD4 TXER/

TXD4

—

CRS CRS —

RXDV RXDV —

RXD2/RMIISEL RXD2 —

RXD3/PHYAD2 RXD3 —

TXCLK TXCLK —

RXCLK/PHYAD1 RXCLK —

XTAL1/CLKIN XTAL1/CLKIN REF_CLK

Note 3-1 In RMII

mode, this pin needs to tied to VSS.

Note 3-2 T

he RXER signal is optional on the RMII bus. This signal is required by the transceiver, but it is

optional for the MAC. The MAC can choose to ignore or not use this signal.