Datasheet

 2016 Microchip Technology Inc. DS00002164B-page 25
LAN8710A/LAN8710AI
3.4.1 MII
The MII includes 16 interface signals:
• transmit data - TXD[3:0]
• transmit strobe - TXEN
• transmit clock - TXCLK
• transmit error - TXER/TXD4
• receive data - RXD[3:0]
• receive strobe - RXDV
• receive clock - RXCLK
• receive error - RXER/RXD4/PHYAD0
• collision indication - COL
• carrier sense - CRS
In MII mode, on the transmit path, the transceiver drives the transmit clock, TXCLK, to the controller. The controller syn-
chronizes the transmit data to the rising edge of TXCLK. The controller drives TXEN high to indicate valid transmit data.
The controller drives TXER high when a transmit error is detected.
On the receive path, the transceiver drives both the receive data, RXD[3:0], and the RXCLK signal. The controller clocks
in the receive data on the rising edge of RXCLK when the transceiver drives RXDV high. The transceiver drives RXER
high when a receive error is detected.
3.4.2 RMII
The device supports the low pin count Reduced Media Independent Interface (RMII) intended for use between Ethernet
transceivers and switch ASICs. Under IEEE 802.3, an MII comprised of 16 pins for data and control is defined. In devices
incorporating many MACs or transceiver interfaces such as switches, the number of pins can add significant cost as the
port counts increase. RMII reduces this pin count while retaining a management interface (MDIO/MDC) that is identical
to MII.
The RMII interface has the following characteristics:
• It is capable of supporting 10Mbps and 100Mbps data rates
• A single clock reference is used for both transmit and receive
• It provides independent 2-bit (di-bit) wide transmit and receive data paths
• It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
The RMII includes the following interface signals (1 optional):
• transmit data - TXD[1:0]
• transmit strobe - TXEN
• receive data - RXD[1:0]
• receive error - RXER (Optional)
• carrier sense - CRS_DV
• Reference Clock - (RMII references usually define this signal as REF_CLK)
3.4.2.1 CRS_DV - Carrier Sense/Receive Data Valid
The CRS_DV is asserted by the device when the receive medium is non-idle. CRS_DV is asserted asynchronously on
detection of carrier due to the criteria relevant to the operating mode. In 10BASE-T mode when squelch is passed, or
in 100BASE-X mode when 2 non-contiguous zeros in 10 bits are detected, the carrier is said to be detected.
Loss of carrier shall result in the deassertion of CRS_DV synchronous to the cycle of REF_CLK which presents the first
di-bit of a nibble onto RXD[1:0] (for example, CRS_DV is deasserted only on nibble boundaries). If the device has addi
-
tional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device shall assert
CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and de-assert CRS_DV on cycles of
REF_CLK which present the first di-bit of a nibble. The result is, starting on nibble boundaries, CRS_DV toggles at 25
MHz in 100Mbps mode and 2.5 MHz in 10Mbps mode when CRS ends before RXDV (for example, the FIFO still has
bits to transfer when the carrier event ends). Therefore, the MAC can accurately recover RXDV and CRS.
During a false carrier event, CRS_DV shall remain asserted for the duration of carrier activity. The data on RXD[1:0] is
considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to
REF_CLK, the data on RXD[1:0] shall be “00” until proper receive signal decoding takes place.