Datasheet

 2007-2016 Microchip Technology Inc. DS00002260A-page 61
LAN8700/LAN8700i
Note 7-3 These levels apply when a 0-3.3V Clock is driven into CLKIN/XTAL1 and XTAL2 is floating. The
maximum input voltage on XTAL1 is VDDIO + 0.4V.
TABLE 7-8: CONFIGURATION INPUTS
Name V
IH
(V) V
IL
(V) I
OH
I
OL
V
OL
(V) V
OH
(V)
SPEED100/PHYAD0 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4
LINK/PHYAD1 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4
ACTIVITY/PHYAD2 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4
FDUPLEX/PHYAD3 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4
CRS/PHYAD4 0.68 * VDDIO 0.4 * VDDIO -8 mA +8 mA +0.4 VDDIO – +0.4
RXD0/MODE0 0.68 * VDDIO 0.4 * VDDIO
RXD1/MODE1 0.68 * VDDIO 0.4 * VDDIO
RXD2/MODE2 0.68 * VDDIO 0.4 * VDDIO
RX_CLK/REGOFF 0.68 * VDDIO 0.4 * VDDIO
COL/RMII/CRS_DV -8 mA +8 mA +0.4 VDDIO – +0.4
TABLE 7-9: GENERAL SIGNALS
Name V
IH
(V) V
IL
(V) I
OH
I
OL
V
OL
(V) V
OH
(V)
nINT/TX_ER/TXD4 -8 mA +8 mA +0.4 VDDIO – +0.4
nRST 0.68 * VDDIO 0.4 * VDDIO
CLKIN/XTAL1 (Note 7-3) +1.40 V 0.4 * VDDIO
XTAL2 - -
NC
TABLE 7-10: ANALOG REFERENCES
Name Buffer Type V
IH
V
IL
I
OH
I
OL
V
OL
V
OH
EXRES1 AI
TABLE 7-11: INTERNAL PULL-UP / PULL-DOWN CONFIGURATIONS
Name Pull-up or Pull-down
SPEED100/PHYAD0 Pull-up
LINK/PHYAD1 Pull-up
ACTIVITY/PHYAD2 Pull-up
FDUPLEX/PHYAD3 Pull-up
CRS/PHYAD4 Pull-up
RXD0/MODE0 Pull-up
RXD1/MODE1 Pull-up
RXD2/MODE2 Pull-up
RXD3/nINTSEL Pull-up
nINT/TX_ER/TXD4 Pull-up
nRST Pull-up
COL/RMII/CRS_DV Pull-down
MDIO Pull-down
MDC Pull-down
RX_CLK/REGOFF Pull-down