Datasheet

LAN8700/LAN8700i
DS00002260A-page 56  2007-2016 Microchip Technology Inc.
6.5 Reset Timing
FIGURE 6-10: RESET TIMING DIAGRAM
TABLE 6-11: RESET TIMING VALUES
Parameter Description MIN TYP MAX Units Notes
T11.1 Reset Pulse Width 100 us
T11.2 Configuration input setup to nRST
rising
200 ns
T11.3 Configuration input hold after
nRST rising
2ns
T11.4 Output Drive after nRST rising 3 800 ns 20 clock cycles for 25
MHz clock
- or -
40 clock cycles for
50MHz clock
nRST
Configuration
Signals
T
11.1
T
11.4
Output drive
T
11.2
T
11.3