2007-2016 Microchip Technology Inc. DS00002260A-page 27
LAN8700/LAN8700i
FIGURE 4-7: MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE
MDC
MDIO
...
32 1's 0 1 10 A4A3A2A1A0R4R3R2R1R0
Write Cycle
D15 D14 D1 D0
...
DataPreamble
Start of
Frame
OP
Code
PHY Address Register Address
Turn
Around
Data To Phy
