Datasheet

LAN8700/LAN8700i

DS00002260A-page 26  2007-2016 Microchip Technology Inc.

4.12.2 I/O VOLTAGE STABILITY

The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance of ± 10%. Varying

the voltage up or down, after the PHY has completed power-on reset can cause errors in the PHY operation.

4.13 PHY Management Control

The Management Control module includes 3 blocks:

• Serial Management Interface (SMI)

• Management Registers Set

• Interrupt

4.13.1 SERIAL MANAGEMENT INTERFACE (SMI)

The Serial Management Interface is used to control the LAN8700/LAN8700i and obtain its status. This interface sup-

ports registers 0 through 6 as required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers 16 to

31 allowed by the specification. Non-supported registers (7 to 15) will be read as hexadecimal “FFFF”.

At the system level there are 2 signals, MDIO and MDC where MDIO is bi-directional open-drain and MDC is the clock.

A special feature (enabled by register 17 bit 3) forces the PHY to disregard the PHY-Address in the SMI packet causing

the PHY to respond to any address. This feature is useful in multi-PHY applications and in production testing, where the

same register can be written in all the PHYs using a single write transaction.

The MDC signal is an aperiodic clock provided by the station management controller (SMC). The MDIO signal receives

serial data (commands) from the controller SMC, and sends serial data (status) to the SMC. The minimum time between

edges of the MDC is 160 ns. There is no maximum time between edges.

The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. These mod-

est timing requirements allow this interface to be easily driven by the I/O port of a microcontroller.

The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown

in Figure 4-6 and Figure 4-7.

The timing relationships of the MDIO signals are further described in Section 6.1, "Serial Management Interface (SMI)

Timing," on page 48.

FIGURE 4-6: MDIO TIMING AND FRAME STRUCTURE - READ CYCLE

MDC

MDI0

Read Cycle

...

32 1's 0110A4A3A2A1A0R4R3R2R1R0

...

D15 D14 D0

Preamble

Start of

Frame

Code

PHY Address Register Address

Turn

Around

Data

Data From Phy

Data To Phy