LAN8700/LAN8700i ±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR® Technology in a Small Footprint Highlights Applications • Single-Chip Ethernet Physical Layer Transceiver (PHY) • ESD Protection levels of ±8kV HBM without external protection devices • ESD protection levels of EN/IEC61000-4-2, ±8kV contact mode, and ±15kV for air discharge mode per independent test facility • Comprehensive flexPWR® Technology - Flexible Power Management Architecture • LVCMOS V
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LAN8700/LAN8700i Table of Contents 1.0 General Description ........................................................................................................................................................................ 4 2.0 Pin Configuration ............................................................................................................................................................................ 6 3.0 Pin Description .................................................................
LAN8700/LAN8700i 1.0 GENERAL DESCRIPTION The Microchip LAN8700/LAN8700i is a low-power, industrial temperature (LAN8700i), variable I/O voltage, analog interface IC with HP Auto-MDIX support for high-performance embedded Ethernet applications. The LAN8700/LAN8700i can be configured to operate on a single 3.3V supply utilizing an integrated 3.3V to 1.8V linear regulator. An option is available to disable the linear regulator to optimize system designs that have a 1.8V power plane available. 1.
LAN8700/LAN8700i FIGURE 1-2: MODE0 MODE1 MODE2 LAN8700/LAN8700I ARCHITECTURAL OVERVIEW MODE Control nRST SMI AutoNegotiation 10M Tx Logic HP Auto-MDIX 10M Transmitter TXP / TXN Transmit Section Management Control 100M Tx Logic MII RXP / RXN 100M Transmitter MDIX Control RXD[0..3] RX_DV RX_ER RX_CLK CRS COL/CRS_DV RMII / MII Logic TXD[0..
LAN8700/LAN8700i 2.0 PIN CONFIGURATION 2.1 Package Pin-out Diagram and Signal Table FIGURE 2-1: PACKAGE PINOUT (TOP VIEW) nINT/TX_ER/TXD4 1 27 TXD3 MDC 2 26 TXD2 CRS/PHYAD4 3 25 VDDIO 24 TXD1 23 TXD0 22 TX_CLK 21 RX_ER/RXD4 MDIO 4 nRST 5 TX_EN 6 LAN8700/LAN8700i MII/RMII Ethernet PHY 36 Pin QFN GND FLAG VDD33 7 VDD_CORE 8 20 RX_CLK/REGOFF SPEED100/PHYAD0 9 19 RX_DV DS00002260A-page 6 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i TABLE 2-1: LAN8700/LAN8700I 36-PIN QFN PINOUT Pin No. Pin Name Pin No. Pin Name 1 nINT/TX_ER/TXD4 19 RX_DV 2 MDC 20 RX_CLK/REGOFF 3 CRS/PHYAD4 21 RX_ER/RXD4 4 MDIO 22 TXCLK 5 nRST 23 TXD0 6 TX_EN 24 TXD1 7 VDD33 25 VDDIO 8 VDD_CORE 26 TXD2 9 SPEED100/PHYAD0 27 TXD3 10 LINK/PHYAD1 28 TXN 11 ACTIVITY/PHYAD2 29 TXP 12 FDUPLEX/PHYAD3 30 VDDA3.3 13 XTAL2 31 RXN 14 CLKIN/XTAL1 32 RXP 15 RXD3/nINTSEL 33 VDDA3.
LAN8700/LAN8700i 3.0 PIN DESCRIPTION This chapter describes the signals on each pin. When a lower case “n” is used at the beginning of the signal name, it indicates that the signal is active low. For example, nRST indicates that the reset signal is active low. 3.1 I/O Signals The following buffer types are shown in the TYPE column of the tables in this chapter. • • • • • • • I IPD O OPD I/O IOPD IOPU Input. Digital LVCMOS levels. Input with internal pull-down. Digital LVCMOS levels. Output.
LAN8700/LAN8700i TABLE 3-1: MII SIGNALS (CONTINUED) Signal Name Type Description RXD0/ MODE0 IOPU Receive Data 0: Bit 0 of the 4 data bits that are sent by the PHY in the receive path. PHY Operating Mode Bit 0: set the default MODE of the PHY. Note: See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 46, for the MODE options RXD1/ MODE1 IOPU Receive Data 1: Bit 1 of the 4 data bits that are sent by the PHY in the receive path. PHY Operating Mode Bit 1: set the default MODE of the PHY.
LAN8700/LAN8700i TABLE 3-1: MII SIGNALS (CONTINUED) Signal Name Type Description RX_CLK/ REGOFF IOPD Receive Clock: In MII mode, this pin is the receive clock output. 25MHz in 100Base-TX mode. 2.5MHz in 10Base-T mode. Note: This signal is not used in RMII Mode. Regulator Off: This pin pulled up to configure the internal 1.8V regulator off. As described in Section 4.9, this pin is sampled during the power-on sequence to determine if the internal regulator should turn on.
LAN8700/LAN8700i TABLE 3-4: Note 3-1 BOOT STRAP CONFIGURATION INPUTS (Note 3-1) Signal Name Type Description CRS/ PHYAD4 IOPU PHY Address Bit 4: set the default address of the PHY. This signal is mux’d with CRS Note: This signal is mux’d with CRS FDUPLEX/ PHYAD3 IOPU PHY Address Bit 3: set the default address of the PHY. Note: This signal is mux’d with FDUPLEX ACTIVITY/ PHYAD2 IOPU PHY Address Bit 2: set the default address of the PHY.
LAN8700/LAN8700i TABLE 3-5: GENERAL SIGNALS Signal Name Type Description nINT/ TX_ER/ TXD4 IOPU LAN Interrupt – Active Low output. Place an external resistor (see Table 4-3, “Boot Strapping Configuration Resistors,” on page 25) pull-up to VCC 3.3V. • This signal is mux’d with TXER/TXD4 • See Section 4.10, "nINT/TX_ER/TXD4 Strapping," on page 24 for additional details on Strapping options. nRST I External Reset – input of the system reset. This signal is active LOW.
LAN8700/LAN8700i TABLE 3-8: POWER SIGNALS Signal Name Type VDDIO POWER Description +1.6V to +3.6V Variable I/O Pad Power VDD33 POWER +3.3V Core Regulator Input. VDDA3.3 POWER +3.3V Analog Power VDD_CORE POWER +1.8V (Core voltage) - 1.8V for digital circuitry on chip. Supplied by the on-chip regulator unless configured for regulator off mode using the RX_CLK/REGOFF pin. Place a 0.1uF capacitor near this pin and connect the capacitor from this pin to ground.
LAN8700/LAN8700i 4.0 ARCHITECTURE DETAILS 4.
LAN8700/LAN8700i TABLE 4-1: 4B/5B CODE TABLE Code Group SYM 11110 0 0 0000 01001 1 1 10100 2 2 10101 3 01010 4 01011 01110 4.2.
LAN8700/LAN8700i 4.2.4 NRZI AND MLT3 ENCODING The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a change in the logic level represents a code bit “1” and the logic output remaining at the same level represents a code bit “0”. 4.2.
LAN8700/LAN8700i 4.3.2 EQUALIZER, BASELINE WANDER CORRECTION AND CLOCK AND DATA RECOVERY The 6 bits from the ADC are fed into the DSP block. The equalizer in the DSP section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and CAT- 5 cable. The equalizer can restore the signal for any good-quality CAT-5 cable between 1m and 150m.
LAN8700/LAN8700i FIGURE 4-3: RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS CLEAR-TEXT J K 5 5 5 D data data data data T R 5 5 5 5 5 D data data data data Idle RX_CLK RX_DV RXD 4.3.8 RECEIVER ERRORS During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RX_ER signal is asserted and arbitrary data is driven onto the RXD[3:0] lines.
LAN8700/LAN8700i For RMII, TXD[1:0] shall transition synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for transmission by the LAN8700/LAN8700i. TXD[1:0] shall be “00” to indicate idle when TX_EN is deasserted. Values of TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signalling (to be defined). Values other than “00” on TXD[1:0] while TX_EN is deasserted shall be ignored by the LAN8700/LAN8700i.
LAN8700/LAN8700i 4.6 MAC Interface The MII/RMII block is responsible for the communication with the controller. Special sets of hand-shake signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit bus. The device must be configured in MII or RMII mode. See Section 4.6.3, "MII vs. RMII Configuration," on page 21. 4.6.
LAN8700/LAN8700i ticity buffering. The elasticity buffer does not affect the Inter-Packet Gap (IPG) for received IPGs of 36 bits or greater. To tolerate the clock variations specified here for Ethernet MTUs, the elasticity buffer shall tolerate a minimum of ±10 bits. 4.6.2.2 CRS_DV - Carrier Sense/Receive Data Valid The CRS_DV is asserted by the LAN8700/LAN8700i when the receive medium is non-idle.
LAN8700/LAN8700i Note 4-1 In RMII mode, this pin needs to tied to VSS. Note 4-2 The RX_ER signal is optional on the RMII bus. This signal is required by the PHY, but it is optional for the MAC. The MAC can choose to ignore or not use this signal. 4.7 Auto-negotiation The purpose of the Auto-negotiation function is to automatically configure the PHY to the optimum link parameters based on the capabilities of its link partner.
LAN8700/LAN8700i Writing register 4 bits [8:5] allows software control of the capabilities advertised by the PHY. Writing register 4 does not automatically re-start auto-negotiation. Register 0, bit 9 must be set before the new abilities will be advertised. Autonegotiation can also be disabled via software by clearing register 0, bit 12. The LAN8700/LAN8700i does not support “Next Page” capability. 4.7.
LAN8700/LAN8700i FIGURE 4-4: 4.9 DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION Internal +1.8V Regulator Disable One feature of the flexPWR technology is the ability to configure the internal 1.8V regulator off. When the regulator is disabled, external 1.8V must be supplied to VDD_CORE. This makes it possible to reduce total system power, since an external switching regulator with greater efficiency than the internal linear regulator may be used to provide the +1.8V to the PHY circuitry. 4.9.
LAN8700/LAN8700i The RXD3/nINTSEL pin is latched on the rising edge of the nRST. The system designer must float the nINTSEL pin to put the nINT/TX_ER/TXD4 pin into nINT mode or pull-low to VSS with an external resistor (see Table 4-3, “Boot Strapping Configuration Resistors,” on page 25) to set the device in TX_ER/TXD4 mode. The default setting is to float the pin high for nINT mode. 4.
LAN8700/LAN8700i 4.12.2 I/O VOLTAGE STABILITY The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance of ± 10%. Varying the voltage up or down, after the PHY has completed power-on reset can cause errors in the PHY operation. 4.13 PHY Management Control The Management Control module includes 3 blocks: • Serial Management Interface (SMI) • Management Registers Set • Interrupt 4.13.
LAN8700/LAN8700i FIGURE 4-7: MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE Write Cycle MDC MDIO 32 1's Preamble 0 1 Start of Frame 0 1 OP Code A4 A3 A2 A1 PHY Address A0 R4 R3 R2 R1 R0 Register Address D15 Turn Around D14 ... ... D1 D0 Data Data To Phy 2007-2016 Microchip Technology Inc.
REGISTERS TABLE 5-1: CONTROL REGISTER: REGISTER 0 (BASIC) 15 14 13 12 11 10 9 8 7 Reset Loopback Speed Select A/N Enable Power Down Isolate Restart A/N Duplex Mode Collision Test TABLE 5-2: 5 4 3 2 1 0 Reserved STATUS REGISTER: REGISTER 1 (BASIC) 15 14 13 12 11 100BaseT4 100BaseTX Full Duplex 100BaseTX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex TABLE 5-3: 15 6 10 9 8 7 6 Reserved 5 4 3 2 1 0 A/N Complete Remote Fault A/N Ability Link Status
2007-2016 Microchip Technology Inc. TABLE 5-6: AUTO-NEGOTIATION LINK PARTNER BASE PAGE ABILITY REGISTER: REGISTER 5 (EXTENDED) 15 14 13 Next Page Acknowledge Remote Fault TABLE 5-7: 15 12 11 Reserved 10 9 8 7 6 5 Pause 100BaseT4 100Base-TX Full Duplex 100BaseTX 10Base-T Full Duplex 10BaseT 14 TABLE 5-8: 13 12 11 10 9 8 7 6 2 1 0 IEEE 802.
15 REGISTER 8 (EXTENDED) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 6 5 4 3 2 1 0 IEEE Reserved TABLE 5-10: 15 14 REGISTER 9 (EXTENDED) 13 12 11 10 9 8 7 IEEE Reserved TABLE 5-11: 15 14 REGISTER 10 (EXTENDED) 13 12 11 10 9 8 7 IEEE Reserved TABLE 5-12: 15 14 REGISTER 11 (EXTENDED) 13 12 11 10 9 8 7 IEEE Reserved 2007-2016 Microchip Technology Inc.
2007-2016 Microchip Technology Inc.
SPECIAL MODES REGISTER 18: VENDOR-SPECIFIC 15 14 Reserved MIIMODE TABLE 5-20: 15 14 13 12 11 10 9 8 7 6 Reserved 5 4 3 2 MODE 1 0 PHYAD RESERVED REGISTER 19: VENDOR-SPECIFIC 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Reserved TABLE 5-21: 15 14 REGISTER 24: VENDOR-SPECIFIC 13 12 11 10 9 8 Reserved TABLE 5-22: 15 14 REGISTER 25: VENDOR-SPECIFIC 13 12 11 10 9 8 Reserved 2007-2016 Microchip Technol
2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i 5.1 SMI Register Mapping The following registers are supported (register numbers are in decimal): TABLE 5-29: SMI REGISTER MAPPING Register # 5.
LAN8700/LAN8700i TABLE 5-30: REGISTER 0 - BASIC CONTROL Address Name Description Mode Default 0.15 Reset 1 = software reset. Bit is self-clearing. For best results, when setting this bit do not set other bits in this register. The configuration (as described in Section 5.4.9.2) is set from the register bit values, and not from the mode pins. RW/ SC 0 0.14 Loopback 1 = loopback mode, 0 = normal operation RW 0 0.13 Speed Select 1 = 100Mbps, 0 = 10Mbps.
LAN8700/LAN8700i TABLE 5-32: REGISTER 2 - PHY IDENTIFIER 1 Address Name 2.15:0 PHY ID Number TABLE 5-33: Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. OUI=00800Fh Mode Default RW 0007h Mode Default REGISTER 3 - PHY IDENTIFIER 2 Address Name 3.15:10 PHY ID Number 3.9:4 Model Number 3.3:0 Revision Number TABLE 5-34: Description Description Assigned to the 19th through 24th RW C0h Six-bit manufacturer’s model number.
LAN8700/LAN8700i TABLE 5-35: REGISTER 5 - AUTO NEGOTIATION LINK PARTNER ABILITY (CONTINUED) Address Name Description Mode Default 5.10 Pause Operation 1 = Pause Operation is supported by remote MAC, 0 = Pause Operation is not supported by remote MAC RO 0 5.9 100Base-T4 1 = T4 able, 0 = no T4 ability. This Phy does not support T4 ability. RO 0 5.8 100Base-TX Full Duplex 1 = TX with full duplex, 0 = no TX full duplex ability RO 0 5.7 100Base-TX 1 = TX able, 0 = no TX ability RO 0 5.
LAN8700/LAN8700i TABLE 5-38: REGISTER 17 - MODE CONTROL/STATUS (CONTINUED) Address Name 17.10 MDPREBP 17.9 FARLOOPBACK 17.8:7 Reserved 17.6 ALTINT Description Mode Default Management Data Preamble Bypass: 0 – detect SMI packets with Preamble 1 – detect SMI packets without preamble RW 0 Force the module to the FAR Loop Back mode, i.e. all the received packets are sent back simultaneously (in 100Base-TX only). This bit is only active in RMII mode.
LAN8700/LAN8700i TABLE 5-40: REGISTER 26 - SYMBOL ERROR COUNTER Address Name Description Mode Default 26.15:0 Sym_Err_Cnt 100Base-TX receiver-based error register that increments when an invalid code symbol is received including IDLE symbols. The counter is incremented only once per packet, even when the received packet contains more than one symbol error. The 16-bit register counts up to 65,536 (216) and rolls over to 0 if incremented beyond that value.
LAN8700/LAN8700i TABLE 5-43: REGISTER 29 - INTERRUPT SOURCE FLAGS (CONTINUED) Address Name 29.1 INT1 29.0 Reserved TABLE 5-44: Description Mode Default 1 = Auto-Negotiation Page Received 0 = not source of interrupt RO/ LH X Ignore on read. RO/ LH 0 Mode Default REGISTER 30 - INTERRUPT MASK Address Name 30.15:8 Reserved Write as 0; ignore on read. RO 0 30.7:1 Mask Bits 1 = interrupt source is enabled 0 = interrupt source is masked RW 0 30.
LAN8700/LAN8700i bit To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 5-46). Then when the event to assert nINT is true, the nINT output will be asserted. When the corresponding Event to De-Assert nINT is true, then the nINT will be de-asserted. TABLE 5-46: Mask INTERRUPT MANAGEMENT Interrupt Source Flag Interrupt Source Event to Assert nINT 30.7 29.7 ENERGYON 17.1 ENERGYON 30.6 29.6 Auto-Negotiation complete 1.
LAN8700/LAN8700i TABLE 5-47: Mask ALTERNATIVE INTERRUPT SYSTEM MANAGEMENT TABLE Interrupt Source Flag Interrupt Source Event to Assert nINT Condition to De-Assert. Bit to Clear nINT 30.7 29.7 ENERGYON 17.1 ENERGYON Rising 17.1 17.1 low 29.7 30.6 29.6 Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising 1.5 1.5 low 29.6 30.5 29.5 Remote Fault Detected 1.4 Remote Fault Rising 1.4 1.4 low 29.5 30.4 29.4 Link Down 1.2 Link Status Falling 1.2 1.2 high 29.4 30.3 29.
LAN8700/LAN8700i 5.4.4 LINK INTEGRITY TEST The LAN8700/LAN8700i performs the link integrity test as outlined in the IEEE 802.3u (Clause 24-15) Link Monitor state diagram. The link status is multiplexed with the 10Mbps link status to form the reportable link status bit in Serial Management Register 1, and is driven to the LINK LED. The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.
LAN8700/LAN8700i Software (SW) reset: Activated by writing register 0, bit 15 high. This signal is self- clearing. After the register-write, internal logic extends the reset by 256µs to allow PLL-stabilization before releasing the logic from reset. The IEEE 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed within 0.5s from the setting of this bit. Power-Down reset: Automatically activated when the PHY comes out of power-down mode.
LAN8700/LAN8700i FIGURE 5-2: NEAR-END LOOPBACK BLOCK DIAGRAM TXD 10/100 Ethernet MAC X RXD Digital Analog X TX RX CAT-5 XFMR Ethernet Transceiver 5.4.8.2 Far Loopback Far loopback is a special test mode for MDI (analog) loopback as indicated by the blue arrows in Figure 5-3. The far loopback mode is enabled by setting bit register 17 bit 9 to logic one. In this mode, data that is received from the link partner on the MDI is looped back out to the link partner.
LAN8700/LAN8700i FIGURE 5-4: 10/100 Ethernet MAC CONNECTOR LOOPBACK BLOCK DIAGRAM TXD RXD RX Digital XFMR Analog Ethernet Transceiver 5.4.9 1 2 3 4 5 6 7 8 TX RJ45 Loopback Cable. Created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6. CONFIGURATION SIGNALS The PHY has 11 configuration signals whose inputs should be driven continuously, either by external logic or external pull-up/pull-down resistors. 5.4.9.
LAN8700/LAN8700i TABLE 5-48: MODE[2:0] BUS (CONTINUED) Default Register Bit Values Mode [2:0] Mode Definitions 110 Power Down mode. In this mode the PHY will wakeup in Power-Down mode. The PHY cannot be used when the MODE[2:0] bits are set to this mode. To exit this mode, the MODE bits in Register 18.7:5 (see Table 5-39) must be configured to some other value and a soft reset must be issued. 111 All capable. Auto-negotiation enabled. 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i 6.0 AC ELECTRICAL CHARACTERISTICS The timing diagrams and limits in this section define the requirements placed on the external signals of the Phy. 6.1 Serial Management Interface (SMI) Timing The Serial Management Interface is used for status and control as described in Section 4.13. FIGURE 6-1: SMI TIMING DIAGRAM T1.1 Clock MDC T1.2 Valid Data (Read from PHY) Data Out MDIO T1.3 Data In MDIO TABLE 6-1: T1.
LAN8700/LAN8700i 6.2 MII 10/100Base-TX/RX Timings 6.2.1 MII 100BASE-T TX/RX TIMINGS 6.2.1.1 100M MII Receive Timing FIGURE 6-2: 100M MII RECEIVE TIMING DIAGRAM Clock Out RX_CLK T2.1 Data Out RXD[3:0] RX_DV RX_ER TABLE 6-2: Parameter T2.2 Valid Data 100M MII RECEIVE TIMING VALUES Description MIN TYP MAX Units T2.1 Receive signals setup to RX_CLK rising 10 ns T2.
LAN8700/LAN8700i 6.2.1.2 100M MII Transmit Timing FIGURE 6-3: 100M MII TRANSMIT TIMING DIAGRAM Clock Out TX_CLK T3.1 Data Out TXD[3:0] TX_EN TX_ER TABLE 6-3: Valid Data 100M MII TRANSMIT TIMING VALUES Parameter T3.1 DS00002260A-page 50 Description MIN TYP MAX Units Transmit signals required setup to TX_CLK rising 12 ns Transmit signals required hold after TX_CLK rising 0 ns TX_CLK frequency 25 MHz TX_CLK Duty-Cycle 40 % Notes 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i 6.2.2 MII 10BASE-T TX/RX TIMINGS 6.2.2.1 10M MII Receive Timing FIGURE 6-4: 10M MII RECEIVE TIMING DIAGRAM Clock Out RX_CLK T4.1 Data Out RXD[3:0] RX_DV TABLE 6-4: Parameter T4.2 Valid Data 10M MII RECEIVE TIMING VALUES Description MIN TYP MAX Units T4.1 Receive signals setup to RX_CLK rising 10 ns T4.2 Receive signals hold from RX_CLK rising 10 ns RX_CLK frequency 2.5 MHz RX_CLK Duty-Cycle 40 % 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i 6.2.2.2 10M MII Transmit Timing FIGURE 6-5: 10M MII TRANSMIT TIMING DIAGRAMS Clock Out TX_CLK T5.1 Data Out TXD[3:0] TX_EN TABLE 6-5: Valid Data 10M MII TRANSMIT TIMING VALUES Parameter Description MIN T5.1 Transmit signals required setup to TX_CLK rising 12 ns Transmit signals required hold after TX_CLK rising 0 ns DS00002260A-page 52 TYP MAX Units TX_CLK frequency 2.5 MHz TX_CLK Duty-Cycle 50 % Notes 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i 6.3 RMII 10/100Base-TX/RX Timings 6.3.1 RMII 100BASE-T TX/RX TIMINGS 6.3.1.1 100M RMII Receive Timing FIGURE 6-6: 100M RMII RECEIVE TIMING DIAGRAM Clock In CLKIN T6.1 Data Out RXD[1:0] CRS_DV TABLE 6-6: Parameter T6.1 Valid Data 100M RMII RECEIVE TIMING VALUES Description Output delay from rising edge of CLKIN to receive signals output valid CLKIN frequency 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i 6.3.1.2 100M RMII Transmit Timing FIGURE 6-7: 100M RMII TRANSMIT TIMING DIAGRAM Clock In CLKIN T8.1 Data Out TXD[1:0] TX_EN TABLE 6-7: T8.2 Valid Data 100M RMII TRANSMIT TIMING VALUES Parameter Description MIN TYP MAX Units T8.1 Transmit signals required setup to rising edge of CLKIN 2 ns T8.2 Transmit signals required hold after rising edge of REF_CLK 1.5 ns CLKIN frequency 6.3.2 50 Notes MHz RMII 10BASE-T TX/RX TIMINGS 6.3.2.
LAN8700/LAN8700i 6.3.2.2 10M RMII Transmit Timing FIGURE 6-9: 10M RMII TRANSMIT TIMING DIAGRAM Clock In CLKIN T 10.2 T 10.1 Data Out TXD[1:0] TX_EN TABLE 6-9: Valid Data 10M RMII TRANSMIT TIMING VALUES Parameter Description MIN T10.1 Transmit signals required setup to rising edge of CLKIN 4 ns T10.2 Transmit signals required hold after rising edge of REF_CLK 2 ns CLKIN frequency 6.
LAN8700/LAN8700i 6.5 Reset Timing FIGURE 6-10: RESET TIMING DIAGRAM T 11.1 nRST T 11.2 T 11.3 Configuration Signals T 11.4 O utput drive TABLE 6-11: RESET TIMING VALUES Parameter Description MIN TYP MAX Units T11.1 Reset Pulse Width 100 us T11.2 Configuration input setup to nRST rising 200 ns T11.3 Configuration input hold after nRST rising 2 ns T11.
LAN8700/LAN8700i 6.6 Clock Circuit LAN8700/LAN8700i can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input for operation in MII mode. If the single-ended clock oscillator method is implemented, XTAL2 should be left unconnected and XTAL1/CLKIN should be driven with a nominal 0-3.3V clock signal. The user is required to supply a 50MHz singleended clock for RMII operation. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
LAN8700/LAN8700i 7.0 DC ELECTRICAL CHARACTERISTICS 7.1 DC Characteristics 7.1.1 MAXIMUM RATINGS Stresses beyond those listed in may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TABLE 7-1: MAXIMUM CONDITIONS Parameter Conditions MIN TYP MAX Units Comment VDD33,VDDIO Power pins to all other pins. -0.5 +3.6 V Digital IO To VSS ground -0.5 +3.6 V VSS VSS to all other pins -0.5 +4.
LAN8700/LAN8700i 7.1.1.2.1 Air Discharge To perform this test, a charged electrode is moved close to the system being tested until a spark is generated. This test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and construction of the test equipment. 7.1.1.2.2 Contact Discharge The uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized.
LAN8700/LAN8700i Note 7-2 7.1.4 Current measurements do not include power applied to the magnetics or the optional external LEDs. Current measurements taken with VDDIO = +3.3V, unless otherwise indicated. DC CHARACTERISTICS - INPUT AND OUTPUT BUFFERS TABLE 7-5: MII BUS INTERFACE SIGNALS Name VIH (V) VIL (V) IOH IOL VOL (V) VOH (V) TXD0 0.68 * VDDIO 0.4 * VDDIO TXD1 0.68 * VDDIO 0.4 * VDDIO TXD2 0.68 * VDDIO 0.4 * VDDIO TXD3 0.68 * VDDIO 0.4 * VDDIO TX_CLK TX_EN 0.68 * VDDIO 0.
LAN8700/LAN8700i TABLE 7-8: CONFIGURATION INPUTS Name VIH (V) VIL (V) IOH IOL VOL (V) VOH (V) SPEED100/PHYAD0 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4 LINK/PHYAD1 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4 ACTIVITY/PHYAD2 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4 FDUPLEX/PHYAD3 0.68 * VDDIO 0.4 * VDDIO -12 mA +12 mA +0.4 VDDIO – +0.4 CRS/PHYAD4 0.68 * VDDIO 0.4 * VDDIO -8 mA +8 mA +0.4 VDDIO – +0.4 RXD0/MODE0 0.
LAN8700/LAN8700i TABLE 7-11: INTERNAL PULL-UP / PULL-DOWN CONFIGURATIONS (CONTINUED) Name Pull-up or Pull-down RX_ER/RXD4 Pull-down RX_DV Pull-down TX_EN Pull-down Note: For VDDIO operation below +2.5V, Microchip recommends designs add external strapping resistors in addition the internal strapping resistors to ensure proper strapped operation.
LAN8700/LAN8700i 8.0 APPLICATION NOTES 8.1 Application Diagram FIGURE 8-1: SIMPLIFIED APPLICATION DIAGRAM (SEE Section 8.4, "Reference Designs") MII/RMII VDD3.3 4.7uF 0.1uF MAC (Media Access Controller) VDD3.3 Voltage Regulator Host System 12.4k 1% RXP RXN VDDA3.3 TXP TXN 31 30 29 28 1 2 3 4 5 6 7 8 32 EXRES1 34 VDDA3.3 VDDA3.3 35 33 COL/RMII/CRS_DV 0.1uF 0.1uF 0.
LAN8700/LAN8700i 8.2 Magnetics Selection For a list of magnetics selected to operate with the Microchip LAN8700, please refer to the Application note “AN 8-13 Suggested Magnetics”. http://ww1.microchip.com/downloads/en/appnotes/en562793.pdf 8.3 Application Notes Application examples are given in pdf format on the Microchip LAN8700 web site. The link to the web site is shown below. http://www.microchip.com/wwwproducts/en/LAN8700 Please check the web site periodically for the latest updates. 8.
LAN8700/LAN8700i 9.0 PACKAGE OUTLINE, TAPE AND REEL 36-PIN QFN PACKAGE, 6 X 6 X 0.9MM BODY, 0.5MM PITCH Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging FIGURE 9-1: 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i FIGURE 9-2: DS00002260A-page 66 QFN, 6X6 TAPE & REEL 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i FIGURE 9-3: Note: REEL DIMENSIONS Standard reel size is 3000 pieces per reel. 2007-2016 Microchip Technology Inc.
LAN8700/LAN8700i APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Level & Date DS00002260A (08-25-16) Rev. 2.3 (04-12-11) Section/Figure/Entry Correction Replaces previous SMSC version Rev. 2.3 (04-12-11) Section 6.5, "Reset Timing," on page 56 Corrected T11.4 minimum value to 3ns. Corrected T11.3 to 2ns.
LAN8700/LAN8700i TABLE A-1: REVISION HISTORY (CONTINUED) Revision Level & Date Section/Figure/Entry Correction Table 6-5, "10M MII Transmit Timing Values" Removed the text “T5.2” in the “Parameter” column. Figure 6-5, "10M MII Transmit Timing Diagrams" Replaced figure. Table 6-3, "100M MII Transmit Timing Values" Removed the text “T3.2” in the “Parameter” column. Figure 6-3, "100M MII Transmit Timing Diagram" Replaced figure. Table 6-11, "Reset Timing Values" Changed the MIN value for T11.
LAN8700/LAN8700i TABLE A-1: REVISION HISTORY (CONTINUED) Revision Level & Date Rev. 1.1 (04-17-07) Rev. 1.0 (04-04-07) DS00002260A-page 70 Section/Figure/Entry Correction Table 5-30, "Register 0 - Basic Control" Corrected Default value for bit 0.11 to the value of 0. This bit does not get set when the MODE[2:0] bits are set to 110. Section 5.4.9.2, "Mode Bus – MODE[2:0]" Added detail about MODE[2:0] pins having no affect at soft reset.
LAN8700/LAN8700i THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
LAN8700/LAN8700i PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
LAN8700/LAN8700i Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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