Datasheet

 2016-2017 Microchip Technology Inc. DS00002117F-page 62
KSZ9031RNX
FIGURE 7-5: POWER-UP/POWER-DOWN/RESET TIMING
Note 1: The recommended power-up sequence is to have the transceiver (AVDDH) and digital I/O (DVDDH) voltages
power up before the 1.2V core (DVDDL, AVDDL, AVDDL_PLL) voltage. If the 1.2V core must power up first, the maxi-
mum lead time for the 1.2V core voltage with respect to the transceiver and digital I/O voltages should be 200 µs.
There is no power sequence requirement between transceiver (AVDDH) and digital I/O (DVDDH) power rails.
The power-up waveforms should be monotonic for all supply voltages to the KSZ9031RNX.
Note 2: After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO)
interface.
Note 3: The recommended power-down sequence is to have the 1.2V core voltage power-down before powering down
the transceiver and digital I/O voltages.
Before the next power-up cycle, all supply voltages to the KSZ9031RNX should reach less than 0.4V and there should
be a minimum wait time of 150 ms from power-off to power-on.
TABLE 7-4: POWER-UP/POWER-DOWN/RESET TIMING PARAMETERS
Timing
Parameter
Description Min. Typ. Max. Units
t
VR
Supply voltages rise time (must be monotonic) 200 — — µs
t
SR
Stable supply voltages to de-assertion of reset 10 — — ms
t
CS
Strap-in pin configuration setup time 5 — —
nst
CH
Strap-in pin configuration hold time 5 — —
t
RC
De-assertion of reset to strap-in pin output 6 — —
t
PC
Supply voltages cycle off-to-on time 150 — — ms
t
SR
t
CS
t
CH
t
RC
SUPPLY
VOLTAGES
RESET_N
STRAP-IN
VALUE
STRAP-IN /
OUTPUT PIN
CORE (DVDDL, AVDDL, AVDDL_PLL)
TRANSCEIVER (AVDDH), DIGITAL I/Os (DVDDH)
t
VR
t
PC
NOTE
1
NOTE
2
NOTE
3