Datasheet

 2016-2017 Microchip Technology Inc. DS00002117F-page 60
KSZ9031RNX
FIGURE 7-3: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
The KSZ9031RNX Fast Link Pulse (FLP) burst-to-burst transmit timing for Auto-Negotiation defaults to 8 ms. IEEE
802.3 Standard specifies this timing to be 16 ms ±8 ms. Some PHY link partners need to receive the FLP with 16 ms
centered timing; otherwise, there can be intermittent link failures and long link-up times.
After KSZ9031RNX power-up/reset, program the following register sequence to set the FLP timing to 16 ms:
1. Write Register Dh = 0x0000 // Set up register address for MMD – Device Address 0h
2. Write Register Eh = 0x0004 // Select Register 4h of MMD – Device Address 0h
3. Write Register Dh = 0x4000 // Select register data for MMD – Device Address 0h, Register 4h
4. Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device Address 0h, Register 4h
5. Write Register Dh = 0x0000 // Set up register address for MMD – Device Address 0h
6. Write Register Eh = 0x0003 // Select Register 3h of MMD – Device Address 0h
7. Write Register Dh = 0x4000 // Select register data for MMD – Device Address 0h, Register 3h
8. Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device Address 0h, Register 3h
9. Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation
The above setting for 16 ms FLP transmit timing is compatible with all PHY link partners.
TABLE 7-2: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS
Timing
Parameter
Description Min. Typ. Max. Units
t
BTB
FLP burst to FLP burst 8 16 24
ms
t
FLPW
FLP burst width — 2 —
t
PW
Clock/Data pulse width — 100 — ns
t
CTD
Clock pulse to data pulse 55.5 64 69.5
µs
t
CTC
Clock pulse to clock pulse 111 128 139
— Number of clock/data pulses per FLP burst 17 — 33 —