Datasheet

KSZ9031RNX
DS00002117F-page 59  2016-2017 Microchip Technology Inc.
The RGMII Version 2.0 Specification defines the RGMII data-to-clock skews only for 1000 Mbps operation, which uses
both clock edges for sampling the data and control signals at the 125 MHz clock frequency (8 ns period). For 10/100
Mbps operations, the data signals are sampled on the rising clock edge and the control signals are sampled on both
clock edges. With slower clock frequencies, 2.5 MHz (400 ns period) for 10 Mbps and 25 MHz (40 ns period) for
100 Mbps, the RGMII data-to-clock skews for 10/100 Mbps operations will have greater timing margins than for
1000 Mbps operation, and therefore can be relaxed from 2.6 ns (maximum) for 1000 Mbps to 160 ns (maximum) for
10 Mbps and 16 ns (maximum) for 100 Mbps.