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ManualsBrandsMicrochip ManualsIntegrated Circuits (ICs)Gigabit Ethernet Transceiver Ethernet/RGMII QFN 67mA
51525354555657585960
2016-2017 Microchip Technology Inc. DS00002117F-page 58
KSZ9031RNX
FIGURE 7-2: RGMII V2.0 SPEC (MULTIPLEXING AND TIMING DIAGRAM – RGMII-ID (V2.0)
WITH INTERNAL CHIP DELAY)
The following notes provide clarification for Figure 7-2.
TXC (SOURCE DATA), solid line, is the MAC GTX_CLK clock output timing per RGMII v1.3 Specification (PCB delay
line required or PHY internal delay required)
TXC (SOURCE DATA) WITH INTERNAL DELAY ADDED, dotted line, is the MAC GTX_CLK clock output timing per
RGMII v2.0 Specification (no PCB delay required and no PHY internal delay required)
RXC (SOURCE DATA), solid line, is the PHY RX_CLK clock output timing per RGMII v1.3 Specification (PCB delay line
required or MAC internal delay required)
RXC (SOURCE DATA) WITH INTERNAL DELAY ADDED, dotted line, is the PHY RX_CLK clock output timing per
RGMII v2.0 Specification (no PCB delay required and no MAC internal delay required)
TABLE 7-1: RGMII V2.0 SPECIFICATION
Parameter Description Min. Typ. Max. Units
T
skew
T Data-to-clock output skew (at transmitter) per
RGMII v1.3 (external delay)
–500 — 500 ps
T
skew
R Data-to-clock input skew (at receiver) per RGMII
v1.3 (external delay)
1.0 — 2.6
ns
T
setup
T Data-to-clock output setup (at transmitter – inte-
grated delay)
1.2 2.0 —
T
hold
T Clock-to-data output hold (at transmitter – inte-
grated delay)
1.2 2.0 —
T
setup
R Data-to-clock input setup (at receiver – integrated
delay)
1.0 2.0 —
T
hold
R Clock-to-data input hold (at receiver – integrated
delay)
1.0 2.0 —
t
cyc
(1000BASE-T) Clock cycle duration for 1000BASE-T 7.2 8.0 8.8
t
cyc
(100BASE-TX) Clock cycle duration for 100BASE-TX 36 40 44
t
cyc
(10BASE-T) Clock cycle duration for 10BASE-T 360 400 440
TXC(SOURCE DATA)
TXC WITH INTERNAL
DELAY ADDED
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CTL
TXC (AT RECEIVER)
RXC (SOURCE DATA)
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CTL
RXC (AT RECEIVER)
TXD[3:0]
TXD[8:5]
TXD[7:4]
T
SETUP
T
T
HOLD
T
T
SETUP
R
T
HOLD
R
TXD[4]
TXEN
TXD[9]
TXERR
RXC WITH INTERNAL
DELAY ADDED
RXD[3:0]
RXD[8:5]
RXD[7:4]
T
SETUP
T
T
HOLD
T
T
SETUP
R
T
HOLD
R
RXD[4]
RXDV
RXD[9]
RXERR